Simulation Results: rstmgr

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.31 %
  • code
  • 99.21 %
  • assert
  • 98.72 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.41 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.150s 67.910us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.230s 62.646us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.070s 37.992us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.720s 135.308us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.290s 45.588us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.760s 95.280us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.070s 37.992us 1 1 100.00
rstmgr_csr_aliasing 1.290s 45.588us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.650s 169.314us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.960s 45.305us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.880s 56.558us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.210s 759.019us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.210s 759.019us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.210s 759.019us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.210s 759.019us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 24.570s 4018.578us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.980s 37.406us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.400s 83.859us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.400s 83.859us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.230s 62.646us 1 1 100.00
rstmgr_csr_rw 1.070s 37.992us 1 1 100.00
rstmgr_csr_aliasing 1.290s 45.588us 1 1 100.00
rstmgr_same_csr_outstanding 1.420s 45.107us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.230s 62.646us 1 1 100.00
rstmgr_csr_rw 1.070s 37.992us 1 1 100.00
rstmgr_csr_aliasing 1.290s 45.588us 1 1 100.00
rstmgr_same_csr_outstanding 1.420s 45.107us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 15.590s 3388.560us 1 1 100.00
rstmgr_tl_intg_err 2.530s 326.620us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 15.590s 3388.560us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 15.590s 3388.560us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.530s 326.620us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.120s 62.253us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.400s 429.179us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.240s 291.460us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 15.590s 3388.560us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.070s 37.992us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.070s 37.992us 1 1 100.00