Simulation Results

Simulation Results: rv_dm/use_dmi_interface

07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.99 %

code
75.83 %

assert
96.35 %

func
91.80 %

block
90.08 %

line
89.93 %

branch
73.09 %

toggle
77.78 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	33.000s	1941.871us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	34.000s	187.205us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	31.000s	350.886us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	33.000s	5096.741us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	31.000s	557.343us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	54.000s	23535.406us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	38.000s	7328.168us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	98.000s	48933.951us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	38.000s	32094.690us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	30.000s	320.049us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	31.000s	615.435us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	30.000s	913.108us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	32.000s	83.690us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	32.000s	638.250us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	31.000s	967.926us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	32.000s	405.797us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	30.000s	285.094us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	30.000s	320.049us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	30.000s	558.095us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	31.000s	311.848us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	30.000s	913.108us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	31.000s	65.925us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	30.000s	257.798us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	31.000s	156.931us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	65.000s	11131.561us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	43.000s	1199.789us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	31.000s	191.526us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	43.000s	1199.789us	1	1	100.00
	rv_dm_csr_rw	31.000s	156.931us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	32.000s	37.996us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	31.000s	114.385us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	33.000s	1941.871us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	32.000s	310.124us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	31.000s	215.841us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	31.000s	622.856us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	35.000s	888.375us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	37.000s	3688.511us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	31.000s	137.932us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	30.000s	220.769us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	69.000s	28959.798us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	32.000s	235.396us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	33.000s	1156.893us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	30.000s	205.533us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	32.000s	66.286us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	37.000s	7879.921us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	102.000s	56122.502us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	30.000s	72.440us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	30.000s	1190.902us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	29.000s	152.615us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	35.000s	865.463us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	35.000s	865.463us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	43.000s	1199.789us	1	1	100.00
	rv_dm_csr_hw_reset	30.000s	257.798us	1	1	100.00
	rv_dm_csr_rw	31.000s	156.931us	1	1	100.00
	rv_dm_same_csr_outstanding	35.000s	1296.575us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	43.000s	1199.789us	1	1	100.00
	rv_dm_csr_hw_reset	30.000s	257.798us	1	1	100.00
	rv_dm_csr_rw	31.000s	156.931us	1	1	100.00
	rv_dm_same_csr_outstanding	35.000s	1296.575us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	33.000s	1879.603us	1	1	100.00
	rv_dm_tl_intg_err	36.000s	3268.674us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	36.000s	3268.674us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	33.000s	1156.893us	1	1	100.00
	rv_dm_debug_disabled	30.000s	265.042us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	33.000s	1156.893us	1	1	100.00
	rv_dm_debug_disabled	30.000s	265.042us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	33.000s	1941.871us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	32.000s	304.348us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	130.561us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	130.561us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	32.000s	304.348us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	33.000s	1685.974us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	150.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	10750988589194924828660495423658461790960284302311278299333744474741608194605	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23873
	rv_dm_autoincr_sba_tl_access	110936397173476014184580610791881693751935716665749471130956896269957979112696	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23907
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	108061400169258203570038965134680832954341343087367560957149668697095852547199	107	UVM_INFO @ 137931919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	17807709050451614259178252124107980899742129355522710310846827124714435286953	107	UVM_INFO @ 220768716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	27033855387847626741557781683524322671682910170681855661353241632202567542020	87	UVM_INFO @ 66285774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	92292773581051178396479947312532393366436730828568680959380234694460393789254	93	UVM_INFO @ 1685973905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	3933999863513233262525161639596670640857580567452534219086794023499448059469	87	UVM_INFO @ 235396198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	78627731992117698842037087940370369654302283080294393228086403934696381784181	99	UVM_INFO @ 1190901673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	1277486520222763448929126529378495380437628896145634637353765376471512655997	87	UVM_INFO @ 83690180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	17517489675052299242759581635310655308626281799853600456065567157754498022717	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---