Simulation Results: rv_timer

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.39 %
  • code
  • 90.39 %
  • assert
  • 96.20 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 72.89 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 746.421us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 28.540us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 43.491us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 183.728us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 16.047us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 19.854us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 43.491us 1 1 100.00
rv_timer_csr_aliasing 2.000s 16.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.000s 165.612us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 3534.140us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 94.000s 329088.829us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 94.000s 329088.829us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.000s 4175.396us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 40.098us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 33.343us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 640.531us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 640.531us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 28.540us 1 1 100.00
rv_timer_csr_rw 1.000s 43.491us 1 1 100.00
rv_timer_csr_aliasing 2.000s 16.047us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 66.449us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 28.540us 1 1 100.00
rv_timer_csr_rw 1.000s 43.491us 1 1 100.00
rv_timer_csr_aliasing 2.000s 16.047us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 66.449us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 39.201us 1 1 100.00
rv_timer_tl_intg_err 1.000s 1087.885us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 1087.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 291.461us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 43.163us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 12.000s 2148.474us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 103708215718887807739073967749278628194817033243459440627563777917350725393009 85
UVM_INFO @ 291461473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 23579510717649720893831691691091628395686354588928028058691426544404519128829 84
UVM_INFO @ 165611867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 77579244781621341093876754804731056489311575906173329022553408112646637151807 84
UVM_INFO @ 43163095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---