Simulation Results: sram_ctrl/main

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.04 %
  • code
  • 94.83 %
  • assert
  • 97.28 %
  • func
  • 93.00 %
  • block
  • 94.96 %
  • line
  • 95.57 %
  • branch
  • 91.91 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 3034.177us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 156.191us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.738us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 224.754us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 24.358us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1446.223us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 16.738us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 24.358us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 174.000s 6156.679us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 49.000s 2850.375us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 18.000s 4891.117us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 163.000s 4599.788us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 119.000s 4495.653us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 35.000s 9015.152us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 2941.917us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 26.000s 6769.741us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 730.604us 1 1 100.00
sram_ctrl_partial_access_b2b 121.000s 4339.779us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 3.000s 668.490us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 691.598us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 2765.938us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 3587.526us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 720.824us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 86.000s 22582.538us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 48.175us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 314.847us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 314.847us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 156.191us 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.738us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 24.358us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.066us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 156.191us 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.738us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 24.358us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 15423.185us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 323.662us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 263.456us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 323.662us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 263.456us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 3587.526us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 3587.526us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.738us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 26.000s 6769.741us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 26.000s 6769.741us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 26.000s 6769.741us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 2941.917us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 1409.544us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 15423.185us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 699.760us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 3034.177us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 3034.177us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 26.000s 6769.741us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 323.662us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 2941.917us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 323.662us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 323.662us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 3034.177us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 323.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 31.000s 2667.303us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 59604529055990495150862261444756165976049399801062678947564057159243143420457 86
UVM_INFO @ 668490423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 38003941376688034745386591489265024998677629862197421121368758069665898150340 86
UVM_INFO @ 691597587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 22171306564163189008835816562814408072314685320228656232838333693909384052631 86
UVM_INFO @ 2765937631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---