Simulation Results: sram_ctrl/ret

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.11 %
  • code
  • 82.11 %
  • assert
  • 97.81 %
  • func
  • 93.40 %
  • block
  • 93.49 %
  • line
  • 94.61 %
  • branch
  • 88.89 %
  • toggle
  • 78.27 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 106.423us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 214.861us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 20.834us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 413.519us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 63.813us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 69.612us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 20.834us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 63.813us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 752.370us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.000s 212.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 1470.980us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 116.000s 3374.929us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 615.738us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 13.000s 890.840us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1873.623us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 517.647us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 171.364us 1 1 100.00
sram_ctrl_partial_access_b2b 84.000s 13037.097us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 38.063us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 26.374us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 121.531us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 4.000s 599.580us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 30.449us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 30.000s 6419.053us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 27.726us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 116.463us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 116.463us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 214.861us 1 1 100.00
sram_ctrl_csr_rw 2.000s 20.834us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 63.813us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 167.135us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 214.861us 1 1 100.00
sram_ctrl_csr_rw 2.000s 20.834us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 63.813us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 167.135us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 235.971us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 923.199us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 154.514us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 923.199us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 154.514us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 599.580us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 599.580us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 20.834us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 517.647us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 517.647us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 517.647us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1873.623us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 122.659us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 235.971us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 125.874us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 106.423us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 106.423us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 517.647us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 923.199us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1873.623us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 923.199us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 923.199us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 106.423us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 923.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 11.000s 1303.588us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 25429762173525762473288199480120408988570779885235745406052742719201613074089 86
UVM_INFO @ 38062771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 75221461590778493878102846466095013568824729458481011000550526116947441931123 86
UVM_INFO @ 26374029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 12841048991068334236210431734695465793459884850183310734009905359712177126237 86
UVM_INFO @ 121531241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---