Simulation Results: uart

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.52 %
  • code
  • 92.73 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 941.507us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 27.631us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 27.329us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 150.218us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 16.081us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 17.170us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 27.329us 1 1 100.00
uart_csr_aliasing 1.000s 16.081us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 46.000s 160029.153us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 941.507us 1 1 100.00
uart_tx_rx 46.000s 160029.153us 1 1 100.00
parity_error 2 2 100.00
uart_intr 73.000s 52957.124us 1 1 100.00
uart_rx_parity_err 39.000s 206448.453us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 46.000s 160029.153us 1 1 100.00
uart_intr 73.000s 52957.124us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 59.000s 153339.902us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 164.000s 106139.364us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 27.000s 218926.037us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 73.000s 52957.124us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 73.000s 52957.124us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 73.000s 52957.124us 1 1 100.00
perf 1 1 100.00
uart_perf 56.000s 19157.768us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 9.000s 1247.141us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 9.000s 1247.141us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.000s 3105.233us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.000s 2702.898us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.000s 1812.568us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 30.000s 6567.818us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 503.000s 105176.165us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 426.000s 107200.401us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 44.719us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 40.144us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 120.466us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 120.466us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 27.631us 1 1 100.00
uart_csr_rw 1.000s 27.329us 1 1 100.00
uart_csr_aliasing 1.000s 16.081us 1 1 100.00
uart_same_csr_outstanding 1.000s 487.711us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 27.631us 1 1 100.00
uart_csr_rw 1.000s 27.329us 1 1 100.00
uart_csr_aliasing 1.000s 16.081us 1 1 100.00
uart_same_csr_outstanding 1.000s 487.711us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 191.164us 1 1 100.00
uart_tl_intg_err 1.000s 46.459us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 46.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 40.000s 18699.626us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 40065050307791904942051097095139046222347563144475376570137352369939789110651 85
UVM_ERROR @ 1163180305 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1163201138 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1254178849 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 1254178849 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0