Simulation Results: aes/gcm_masked

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.84 %
  • code
  • 96.18 %
  • assert
  • 98.14 %
  • func
  • 66.21 %
  • block
  • 96.54 %
  • line
  • 97.63 %
  • branch
  • 91.63 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
94.74%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 10.000s 890.434us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 68.351us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 84.248us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 53.957us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 526.566us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 102.238us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 85.657us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 53.957us 1 1 100.00
aes_csr_aliasing 2.000s 102.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 68.351us 1 1 100.00
aes_config_error 2.000s 91.254us 1 1 100.00
aes_stress 3.000s 841.658us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 68.351us 1 1 100.00
aes_config_error 2.000s 91.254us 1 1 100.00
aes_stress 3.000s 841.658us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 841.658us 1 1 100.00
aes_b2b 11.000s 883.347us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 841.658us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 68.351us 1 1 100.00
aes_config_error 2.000s 91.254us 1 1 100.00
aes_stress 3.000s 841.658us 1 1 100.00
aes_alert_reset 3.000s 70.314us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 135.799us 1 1 100.00
aes_config_error 2.000s 91.254us 1 1 100.00
aes_alert_reset 3.000s 70.314us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 110.179us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 562.432us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 348.949us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 70.314us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 841.658us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 841.658us 1 1 100.00
aes_sideload 7.000s 277.628us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 113.413us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.118s 0.000us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 234.909us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 54.241us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 266.367us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 266.367us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 84.248us 1 1 100.00
aes_csr_rw 1.000s 53.957us 1 1 100.00
aes_csr_aliasing 2.000s 102.238us 1 1 100.00
aes_same_csr_outstanding 1.000s 62.886us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 84.248us 1 1 100.00
aes_csr_rw 1.000s 53.957us 1 1 100.00
aes_csr_aliasing 2.000s 102.238us 1 1 100.00
aes_same_csr_outstanding 1.000s 62.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 6.000s 434.949us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 7.000s 193.777us 0 1 0.00
aes_control_fi 2.000s 62.224us 1 1 100.00
aes_cipher_fi 2.000s 72.393us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 67.032us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 67.032us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 67.032us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 67.032us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 190.102us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 2933.030us 1 1 100.00
aes_tl_intg_err 2.000s 158.155us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 158.155us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 70.314us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 67.032us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 67.032us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 68.351us 1 1 100.00
aes_stress 3.000s 841.658us 1 1 100.00
aes_alert_reset 3.000s 70.314us 1 1 100.00
aes_core_fi 3.000s 93.116us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 234.909us 1 1 100.00
aes_config_error 2.000s 91.254us 1 1 100.00
aes_stress 3.000s 841.658us 1 1 100.00
aes_core_fi 3.000s 93.116us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 67.032us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 109.826us 1 1 100.00
aes_stress 3.000s 841.658us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 841.658us 1 1 100.00
aes_sideload 7.000s 277.628us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 109.826us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 109.826us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 109.826us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 109.826us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 109.826us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 841.658us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 841.658us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 7.000s 193.777us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 7.000s 193.777us 0 1 0.00
aes_control_fi 2.000s 62.224us 1 1 100.00
aes_cipher_fi 2.000s 72.393us 1 1 100.00
aes_ctr_fi 2.000s 80.823us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 7.000s 193.777us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 7.000s 193.777us 0 1 0.00
aes_control_fi 2.000s 62.224us 1 1 100.00
aes_cipher_fi 2.000s 72.393us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 72.393us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 7.000s 193.777us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 7.000s 193.777us 0 1 0.00
aes_control_fi 2.000s 62.224us 1 1 100.00
aes_ctr_fi 2.000s 80.823us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 7.000s 193.777us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 7.000s 193.777us 0 1 0.00
aes_control_fi 2.000s 62.224us 1 1 100.00
aes_cipher_fi 2.000s 72.393us 1 1 100.00
aes_ctr_fi 2.000s 80.823us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 70.314us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 7.000s 193.777us 0 1 0.00
aes_control_fi 2.000s 62.224us 1 1 100.00
aes_cipher_fi 2.000s 72.393us 1 1 100.00
aes_ctr_fi 2.000s 80.823us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 7.000s 193.777us 0 1 0.00
aes_control_fi 2.000s 62.224us 1 1 100.00
aes_cipher_fi 2.000s 72.393us 1 1 100.00
aes_ctr_fi 2.000s 80.823us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 7.000s 193.777us 0 1 0.00
aes_control_fi 2.000s 62.224us 1 1 100.00
aes_ctr_fi 2.000s 80.823us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 91.053us 1 1 100.00
aes_fi 7.000s 193.777us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 7.000s 193.777us 0 1 0.00
aes_control_fi 2.000s 62.224us 1 1 100.00
aes_cipher_fi 2.000s 72.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 20.949us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 85947592952155124367340433757066864554736737732300956644768236059035310195981 41621
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_stress_all 104772306903037166135793777459118073955412848050004779875552035349973715210930 None
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 112702033089048655374808148925196530429972721745598704830853338931746033560867 140
UVM_INFO @ 20948529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---