Simulation Results: aes/gcm_unmasked

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.11 %
  • code
  • 90.66 %
  • assert
  • 97.94 %
  • func
  • 63.73 %
  • block
  • 90.77 %
  • line
  • 92.79 %
  • branch
  • 83.20 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 66.684us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 63.963us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 100.943us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 69.512us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 9.000s 4152.092us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 973.178us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 231.133us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 69.512us 1 1 100.00
aes_csr_aliasing 3.000s 973.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 63.963us 1 1 100.00
aes_config_error 2.000s 220.515us 1 1 100.00
aes_stress 2.000s 92.925us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 63.963us 1 1 100.00
aes_config_error 2.000s 220.515us 1 1 100.00
aes_stress 2.000s 92.925us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 92.925us 1 1 100.00
aes_b2b 5.000s 199.198us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 92.925us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 63.963us 1 1 100.00
aes_config_error 2.000s 220.515us 1 1 100.00
aes_stress 2.000s 92.925us 1 1 100.00
aes_alert_reset 2.000s 992.356us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 95.377us 1 1 100.00
aes_config_error 2.000s 220.515us 1 1 100.00
aes_alert_reset 2.000s 992.356us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 126.243us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 450.548us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 992.356us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 92.925us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 92.925us 1 1 100.00
aes_sideload 2.000s 125.668us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 158.859us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 3.000s 38.043us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 94.980us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 146.248us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 146.248us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 100.943us 1 1 100.00
aes_csr_rw 2.000s 69.512us 1 1 100.00
aes_csr_aliasing 3.000s 973.178us 1 1 100.00
aes_same_csr_outstanding 2.000s 145.868us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 100.943us 1 1 100.00
aes_csr_rw 2.000s 69.512us 1 1 100.00
aes_csr_aliasing 3.000s 973.178us 1 1 100.00
aes_same_csr_outstanding 2.000s 145.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 173.644us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 206.192us 0 1 0.00
aes_control_fi 2.000s 56.198us 1 1 100.00
aes_cipher_fi 1.000s 53.097us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 222.324us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 222.324us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 222.324us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 222.324us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 310.567us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 911.251us 1 1 100.00
aes_tl_intg_err 3.000s 382.726us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 382.726us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 992.356us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 222.324us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 222.324us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 63.963us 1 1 100.00
aes_stress 2.000s 92.925us 1 1 100.00
aes_alert_reset 2.000s 992.356us 1 1 100.00
aes_core_fi 2.000s 103.160us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 220.515us 1 1 100.00
aes_stress 2.000s 92.925us 1 1 100.00
aes_core_fi 2.000s 103.160us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 222.324us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 56.092us 1 1 100.00
aes_stress 2.000s 92.925us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 92.925us 1 1 100.00
aes_sideload 2.000s 125.668us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 56.092us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 56.092us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 56.092us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 56.092us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 56.092us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 92.925us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 92.925us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 206.192us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 206.192us 0 1 0.00
aes_control_fi 2.000s 56.198us 1 1 100.00
aes_cipher_fi 1.000s 53.097us 1 1 100.00
aes_ctr_fi 2.000s 61.102us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 206.192us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 206.192us 0 1 0.00
aes_control_fi 2.000s 56.198us 1 1 100.00
aes_cipher_fi 1.000s 53.097us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 53.097us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 206.192us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 206.192us 0 1 0.00
aes_control_fi 2.000s 56.198us 1 1 100.00
aes_ctr_fi 2.000s 61.102us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 206.192us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 206.192us 0 1 0.00
aes_control_fi 2.000s 56.198us 1 1 100.00
aes_cipher_fi 1.000s 53.097us 1 1 100.00
aes_ctr_fi 2.000s 61.102us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 992.356us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 206.192us 0 1 0.00
aes_control_fi 2.000s 56.198us 1 1 100.00
aes_cipher_fi 1.000s 53.097us 1 1 100.00
aes_ctr_fi 2.000s 61.102us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 206.192us 0 1 0.00
aes_control_fi 2.000s 56.198us 1 1 100.00
aes_cipher_fi 1.000s 53.097us 1 1 100.00
aes_ctr_fi 2.000s 61.102us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 206.192us 0 1 0.00
aes_control_fi 2.000s 56.198us 1 1 100.00
aes_ctr_fi 2.000s 61.102us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 206.192us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 206.192us 0 1 0.00
aes_control_fi 2.000s 56.198us 1 1 100.00
aes_cipher_fi 1.000s 53.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 19.000s 1244.508us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 96442597993697661244889839442994487354518235341754066842175195349589594555206 9058
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1143): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) 1 test run
aes_stress_all 41250408755074636249438550815355304354274750921131408395065306442016957212895 9983
UVM_ERROR @ 38042636 ps: (aes_core.sv:1143) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 38042636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 23476009449360669999952643233579138383857725151951680732299266199879063271469 602
UVM_INFO @ 1244508157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---