Simulation Results: alert_handler

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.05 %
  • code
  • 91.56 %
  • assert
  • 98.38 %
  • func
  • 77.20 %
  • line
  • 99.76 %
  • branch
  • 98.18 %
  • cond
  • 91.48 %
  • toggle
  • 87.72 %
  • FSM
  • 80.65 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 13.180s 1032.602us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.310s 73.251us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.720s 136.378us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 242.670s 27371.696us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 48.450s 3517.382us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.310s 44.279us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.720s 136.378us 1 1 100.00
alert_handler_csr_aliasing 48.450s 3517.382us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 134.580s 13188.812us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 22.340s 2818.123us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1643.600s 737160.779us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 33.630s 1864.761us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 13.180s 1032.602us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 16.530s 1210.992us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 60.930s 1482.287us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 21.510s 1329.736us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1317.860s 68868.483us 1 1 100.00
alert_handler_lpg_stub_clk 1724.160s 83839.145us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2680.210s 286929.894us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 11.850s 1435.264us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.420s 50.388us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.450s 22.251us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.020s 290.890us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.020s 290.890us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.310s 73.251us 1 1 100.00
alert_handler_csr_rw 4.720s 136.378us 1 1 100.00
alert_handler_csr_aliasing 48.450s 3517.382us 1 1 100.00
alert_handler_same_csr_outstanding 17.120s 323.554us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.310s 73.251us 1 1 100.00
alert_handler_csr_rw 4.720s 136.378us 1 1 100.00
alert_handler_csr_aliasing 48.450s 3517.382us 1 1 100.00
alert_handler_same_csr_outstanding 17.120s 323.554us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 138.620s 10565.905us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 138.620s 10565.905us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 138.620s 10565.905us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 138.620s 10565.905us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 491.520s 21233.475us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 17.990s 996.715us 1 1 100.00
alert_handler_tl_intg_err 3.300s 34.814us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.300s 34.814us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 138.620s 10565.905us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 13.180s 1032.602us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 13.180s 1032.602us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 13.180s 1032.602us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 13.180s 1032.602us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 33.630s 1864.761us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1317.860s 68868.483us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 33.630s 1864.761us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1643.600s 737160.779us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1643.600s 737160.779us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.990s 996.715us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.990s 996.715us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.990s 996.715us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.990s 996.715us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 17.990s 996.715us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.990s 996.715us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.990s 996.715us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.990s 996.715us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 17.990s 996.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 100.390s 21158.263us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. 1 test run
alert_handler_ping_timeout 114863860880233856457929096276544919653330895740484052819336569139778743047391 80
UVM_INFO @ 1329736059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 54022608208854156559520723919664697909758137803785230732867607623661196365659 162
UVM_INFO @ 1435263639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 60968700582020223526621296317116906215899627734455888366826676415380998669454 118
UVM_INFO @ 21158262965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---