Simulation Results: clkmgr

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.90 %
  • code
  • 75.48 %
  • assert
  • 90.70 %
  • func
  • 61.52 %
  • line
  • 89.61 %
  • branch
  • 92.54 %
  • cond
  • 84.26 %
  • toggle
  • 98.49 %
  • FSM
  • 12.50 %
Validation stages
V1
50.00%
V2
61.54%
V2S
25.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.430s 104.386us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.860s 23.194us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.630s 2.677us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 4.530s 397.089us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.270s 37.967us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.650s 2.011us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.630s 2.677us 0 1 0.00
clkmgr_csr_aliasing 1.270s 37.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.990s 23.415us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.010s 33.312us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.960s 36.197us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.430s 104.386us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.690s 5.516us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.650s 4.901us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.690s 5.516us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.210s 61.969us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.410s 61.206us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 5.010s 531.196us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 5.010s 531.196us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.860s 23.194us 1 1 100.00
clkmgr_csr_rw 0.630s 2.677us 0 1 0.00
clkmgr_csr_aliasing 1.270s 37.967us 1 1 100.00
clkmgr_same_csr_outstanding 0.960s 25.018us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.860s 23.194us 1 1 100.00
clkmgr_csr_rw 0.630s 2.677us 0 1 0.00
clkmgr_csr_aliasing 1.270s 37.967us 1 1 100.00
clkmgr_same_csr_outstanding 0.960s 25.018us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 96.500s 10150.557us 0 1 0.00
clkmgr_tl_intg_err 0.720s 5.487us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 110.123us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 110.123us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 110.123us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 110.123us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.810s 4.817us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.720s 5.487us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.690s 5.516us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.650s 4.901us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 110.123us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.900s 33.594us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.630s 2.677us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 96.500s 10150.557us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.630s 2.677us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.630s 2.677us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 96.500s 10150.557us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 0.800s 25.302us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.890s 5.635us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 62987888813510398176493323409262313138155304893543998088704463343809548347331 75
UVM_INFO @ 4816633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 101790558043737607458146450011978790791772362189135936901258182336818804680369 75
UVM_INFO @ 2677107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 4160836879118488527603251257217403557746301029088402643331591737311629834861 76
UVM_INFO @ 2011171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 12097453277346816656306026307850668915064533518313292954231232522361915404771 75
UVM_INFO @ 5516308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 57757751311531584199393098595945302920749921019654978998827315511692762619552 77
UVM_INFO @ 5634910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 106845487588101376412471867078392201466572954020745032581823503046963517213663 78
UVM_INFO @ 4900833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 50389426529106357788842302543254556844603998694483552072578496572064707792127 126
UVM_INFO @ 61969167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 11863587523876788399677423835164686243288362826394043781978072990005966947954 203
UVM_INFO @ 10150556776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 1 test run
clkmgr_tl_intg_err 38346443141972946937409167184251688457993558297302113088789801340937685786549 83
UVM_INFO @ 5487381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 79411266589856561743994214411828366732279641441627628018686398107351040865932 75
UVM_INFO @ 397088781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 99126368300105767857044515924656352024759026106647557488126227345805331769513 76
UVM_INFO @ 25017683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---