Simulation Results: dma

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.35 %
  • code
  • 89.70 %
  • assert
  • 96.61 %
  • func
  • 60.73 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 88.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 10.000s 567.644us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 1260.151us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 583.124us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 394.790us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 19.441us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 8.000s 948.466us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 344.124us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 149.756us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 19.441us 1 1 100.00
dma_csr_aliasing 3.000s 344.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 62.000s 20512.993us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 209.000s 29478.243us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 121.000s 12691.135us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 121.000s 12691.135us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 209.000s 29478.243us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 678.000s 73558.320us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 121.000s 12691.135us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 9.000s 561.959us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 40.000s 4403.401us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 109.497us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 46.480us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 158.851us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 158.851us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 394.790us 1 1 100.00
dma_csr_rw 1.000s 19.441us 1 1 100.00
dma_csr_aliasing 3.000s 344.124us 1 1 100.00
dma_same_csr_outstanding 1.000s 72.198us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 394.790us 1 1 100.00
dma_csr_rw 1.000s 19.441us 1 1 100.00
dma_csr_aliasing 3.000s 344.124us 1 1 100.00
dma_same_csr_outstanding 1.000s 72.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 11.000s 3860.072us 1 1 100.00
dma_generic_stress 678.000s 73558.320us 1 1 100.00
dma_handshake_stress 121.000s 12691.135us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 4.000s 1117.773us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 404.876us 1 1 100.00
dma_sec_cm 1.000s 41.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 104.000s 12358.432us 1 1 100.00
dma_longer_transfer 17.000s 1270.308us 1 1 100.00
dma_stress_all_with_rand_reset 21.000s 3497.609us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 34311452442446611276471853105722404490841708594428618247968382269233383189104 160
UVM_INFO @ 3497608696ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---