Simulation Results: edn/edn0

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.38 %
  • code
  • 82.52 %
  • assert
  • 94.25 %
  • func
  • 49.37 %
  • block
  • 93.47 %
  • line
  • 96.49 %
  • branch
  • 85.98 %
  • toggle
  • 71.64 %
  • FSM
  • 75.97 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 20.562us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 19.767us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 44.478us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 1302.598us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 103.458us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 539.320us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 44.478us 1 1 100.00
edn_csr_aliasing 1.000s 103.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 144.176us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 144.176us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 144.176us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 28.159us 1 1 100.00
alerts 1 1 100.00
edn_alert 3.000s 34.867us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 19.932us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 14.243us 1 1 100.00
edn_disable_auto_req_mode 2.000s 67.144us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 77.852us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 52.672us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 20.248us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 166.674us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 166.674us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 19.767us 1 1 100.00
edn_csr_rw 2.000s 44.478us 1 1 100.00
edn_csr_aliasing 1.000s 103.458us 1 1 100.00
edn_same_csr_outstanding 2.000s 82.036us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 19.767us 1 1 100.00
edn_csr_rw 2.000s 44.478us 1 1 100.00
edn_csr_aliasing 1.000s 103.458us 1 1 100.00
edn_same_csr_outstanding 2.000s 82.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 8.000s 2024.409us 1 1 100.00
edn_tl_intg_err 2.000s 96.110us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 20.439us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 3.000s 34.867us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.000s 2024.409us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.000s 2024.409us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 8.000s 2024.409us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 8.000s 2024.409us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 3.000s 34.867us 1 1 100.00
edn_sec_cm 8.000s 2024.409us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 3.000s 34.867us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 96.110us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 27.000s 6097.106us 1 1 100.00