Simulation Results: edn/edn1

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.85 %
  • code
  • 84.60 %
  • assert
  • 98.70 %
  • func
  • 80.25 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 90.15 %
  • toggle
  • 95.70 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.800s 71.992us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.730s 46.836us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.840s 16.252us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.790s 560.189us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.050s 32.560us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.160s 30.302us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.840s 16.252us 1 1 100.00
edn_csr_aliasing 1.050s 32.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.270s 41.648us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.270s 41.648us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.270s 41.648us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.960s 29.218us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.090s 113.993us 1 1 100.00
errs 1 1 100.00
edn_err 0.740s 36.306us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 41.654us 1 1 100.00
edn_disable_auto_req_mode 0.960s 121.042us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.600s 323.758us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 38.340us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.990s 40.313us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.780s 95.762us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.780s 95.762us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.730s 46.836us 1 1 100.00
edn_csr_rw 0.840s 16.252us 1 1 100.00
edn_csr_aliasing 1.050s 32.560us 1 1 100.00
edn_same_csr_outstanding 0.860s 85.580us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.730s 46.836us 1 1 100.00
edn_csr_rw 0.840s 16.252us 1 1 100.00
edn_csr_aliasing 1.050s 32.560us 1 1 100.00
edn_same_csr_outstanding 0.860s 85.580us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.980s 2850.784us 1 1 100.00
edn_tl_intg_err 1.440s 54.804us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.830s 18.114us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.090s 113.993us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.980s 2850.784us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.980s 2850.784us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.980s 2850.784us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.980s 2850.784us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.090s 113.993us 1 1 100.00
edn_sec_cm 2.980s 2850.784us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.090s 113.993us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.440s 54.804us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 43.160s 2838.817us 1 1 100.00