| V1 |
|
83.33% |
| V2 |
|
87.50% |
| V2S |
|
85.71% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| entropy_src_smoke | 2.000s | 25.011us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 77.798us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 66.140us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| entropy_src_csr_bit_bash | 7.000s | 2405.670us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| entropy_src_csr_aliasing | 3.000s | 272.857us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_csr_mem_rw_with_rand_reset | 1.000s | 15.201us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 66.140us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 272.857us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 2 | 3 | 66.67 | |||
| entropy_src_smoke | 2.000s | 25.011us | 1 | 1 | 100.00 | |
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 301.000s | 12696.488us | 0 | 1 | 0.00 | |
| firmware_mode | 0 | 1 | 0.00 | |||
| entropy_src_fw_ov | 301.000s | 12696.488us | 0 | 1 | 0.00 | |
| rng_mode | 1 | 1 | 100.00 | |||
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| rng_max_rate | 0 | 1 | 0.00 | |||
| entropy_src_rng_max_rate | 107.000s | 2954.280us | 0 | 1 | 0.00 | |
| health_checks | 1 | 1 | 100.00 | |||
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| conditioning | 1 | 1 | 100.00 | |||
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| interrupts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| entropy_src_intr | 19.000s | 809.733us | 1 | 1 | 100.00 | |
| alerts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| entropy_src_functional_alerts | 5.000s | 358.297us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| entropy_src_stress_all | 313.000s | 14146.476us | 1 | 1 | 100.00 | |
| functional_errors | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 109.529us | 1 | 1 | 100.00 | |
| firmware_ov_read_contiguous_data | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov_contiguous | 2.000s | 38.620us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| entropy_src_intr_test | 2.000s | 23.645us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| entropy_src_alert_test | 2.000s | 61.821us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 5.000s | 142.834us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 5.000s | 142.834us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 77.798us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 66.140us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 272.857us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 2.000s | 77.093us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 77.798us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 66.140us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 272.857us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 2.000s | 77.093us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| entropy_src_sec_cm | 2.000s | 61.082us | 1 | 1 | 100.00 | |
| entropy_src_tl_intg_err | 3.000s | 371.050us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 2 | 2 | 100.00 | |||
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| entropy_src_cfg_regwen | 2.000s | 41.802us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 1 | 1 | 100.00 | |||
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| sec_cm_config_redun | 1 | 1 | 100.00 | |||
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 2 | 50.00 | |||
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 301.000s | 12696.488us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 109.529us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 61.082us | 1 | 1 | 100.00 | |
| sec_cm_ack_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 109.529us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 61.082us | 1 | 1 | 100.00 | |
| sec_cm_rng_bkgn_chk | 1 | 1 | 100.00 | |||
| entropy_src_rng | 85.000s | 13231.693us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 109.529us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 61.082us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 109.529us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 61.082us | 1 | 1 | 100.00 | |
| sec_cm_ctr_local_esc | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 109.529us | 1 | 1 | 100.00 | |
| sec_cm_esfinal_rdata_bus_consistency | 1 | 1 | 100.00 | |||
| entropy_src_functional_alerts | 5.000s | 358.297us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| entropy_src_tl_intg_err | 3.000s | 371.050us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| external_health_tests | 1 | 1 | 100.00 | |||
| entropy_src_rng_with_xht_rsps | 314.000s | 13037.607us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_stress_all_with_rand_reset | 3.000s | 30.512us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (entropy_src_scoreboard.sv:2942) [scoreboard] Check failed prediction == csr_val (* [*] vs * [*]) Prediction for observe FIFO access failed. | 1 test run | |||
| entropy_src_rng_max_rate | 115531379973896092489864270077652546858770212524833811129050729292635618220223 | 1317 |
UVM_INFO @ 2954279796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold | 1 test run | |||
| entropy_src_stress_all_with_rand_reset | 114790335881281933180269563998037482454481632593830899700422828608796527877089 | 114 |
UVM_INFO @ 30511544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (entropy_src_scoreboard.sv:2115) [scoreboard] Check failed fw_ov_wr_fifo_full_prediction == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.fw_ov_wr_fifo_full | 1 test run | |||
| entropy_src_fw_ov | 91466070011431988694538214550655480495503556695861955892901341619167251382978 | 1765 |
UVM_INFO @ 12696487754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts | 1 test run | |||
| entropy_src_csr_mem_rw_with_rand_reset | 42157818571372733838694434275423588229975541258261179271400430602386906014787 | 113 |
UVM_INFO @ 15200574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|