Simulation Results: hmac

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.09 %
  • code
  • 96.03 %
  • assert
  • 97.17 %
  • func
  • 29.06 %
  • block
  • 97.55 %
  • line
  • 98.44 %
  • branch
  • 93.88 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.000s 197.532us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 252.804us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 19.877us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.000s 1773.562us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 197.236us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 24.756us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 19.877us 1 1 100.00
hmac_csr_aliasing 5.000s 197.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 8.000s 2725.612us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 93.000s 11645.537us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 239.000s 9361.337us 1 1 100.00
hmac_test_sha384_vectors 24.000s 1264.754us 1 1 100.00
hmac_test_sha512_vectors 474.000s 87289.737us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 1254.214us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 2217.804us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 753.586us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.000s 956.837us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 165.000s 5261.276us 1 1 100.00
error 1 1 100.00
hmac_error 78.000s 29231.508us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 70.000s 30048.051us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.000s 197.532us 1 1 100.00
hmac_long_msg 8.000s 2725.612us 1 1 100.00
hmac_back_pressure 93.000s 11645.537us 1 1 100.00
hmac_datapath_stress 165.000s 5261.276us 1 1 100.00
hmac_burst_wr 15.000s 956.837us 1 1 100.00
hmac_stress_all 766.000s 622861.633us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.000s 197.532us 1 1 100.00
hmac_long_msg 8.000s 2725.612us 1 1 100.00
hmac_back_pressure 93.000s 11645.537us 1 1 100.00
hmac_datapath_stress 165.000s 5261.276us 1 1 100.00
hmac_wipe_secret 70.000s 30048.051us 1 1 100.00
hmac_test_sha256_vectors 239.000s 9361.337us 1 1 100.00
hmac_test_sha384_vectors 24.000s 1264.754us 1 1 100.00
hmac_test_sha512_vectors 474.000s 87289.737us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 1254.214us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 2217.804us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 753.586us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.000s 197.532us 1 1 100.00
hmac_long_msg 8.000s 2725.612us 1 1 100.00
hmac_back_pressure 93.000s 11645.537us 1 1 100.00
hmac_datapath_stress 165.000s 5261.276us 1 1 100.00
hmac_burst_wr 15.000s 956.837us 1 1 100.00
hmac_error 78.000s 29231.508us 1 1 100.00
hmac_wipe_secret 70.000s 30048.051us 1 1 100.00
hmac_test_sha256_vectors 239.000s 9361.337us 1 1 100.00
hmac_test_sha384_vectors 24.000s 1264.754us 1 1 100.00
hmac_test_sha512_vectors 474.000s 87289.737us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 1254.214us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 2217.804us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 753.586us 1 1 100.00
hmac_stress_all 766.000s 622861.633us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 766.000s 622861.633us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 14.181us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 32.663us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 50.457us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 50.457us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 252.804us 1 1 100.00
hmac_csr_rw 2.000s 19.877us 1 1 100.00
hmac_csr_aliasing 5.000s 197.236us 1 1 100.00
hmac_same_csr_outstanding 2.000s 440.513us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 252.804us 1 1 100.00
hmac_csr_rw 2.000s 19.877us 1 1 100.00
hmac_csr_aliasing 5.000s 197.236us 1 1 100.00
hmac_same_csr_outstanding 2.000s 440.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 923.192us 1 1 100.00
hmac_tl_intg_err 4.000s 134.756us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 134.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.000s 197.532us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 1289.744us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 94.000s 30563.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 83.889us 1 1 100.00