Simulation Results

Simulation Results: i2c

08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.58 %

code
86.43 %

assert
96.41 %

func
79.90 %

block
96.25 %

line
95.62 %

branch
93.30 %

toggle
72.64 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	38.000s	5503.630us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	10.000s	1972.070us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	139.995us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	162.013us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.000s	347.302us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	3.000s	59.912us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	111.533us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	162.013us	1	1	100.00
	i2c_csr_aliasing	3.000s	59.912us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	96.410us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	2.000s	315.116us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	90.000s	27872.001us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	49.721us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	2190.000s	10793.121us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	948.000s	1844.127us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	343.711us	1	1	100.00
	i2c_host_fifo_fmt_empty	11.000s	1002.658us	1	1	100.00
	i2c_host_fifo_reset_rx	7.000s	563.617us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	47.000s	2873.606us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	23.000s	2405.660us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	23.671us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.000s	978.274us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	9.000s	4207.440us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	34.000s	4417.760us	1	1	100.00
	i2c_target_intr_smoke	9.000s	5878.751us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	276.863us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	272.187us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	3248.000s	53338.387us	1	1	100.00
	i2c_target_stress_rd	34.000s	4417.760us	1	1	100.00
	i2c_target_intr_stress_wr	2412.000s	9336.281us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	9.000s	1392.150us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	245.000s	5557.982us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.000s	1014.139us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	14.000s	10083.733us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.000s	170.922us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	137.200us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	90.000s	27872.001us	1	1	100.00
	i2c_host_perf_precise	3.000s	266.175us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	23.000s	2405.660us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	8.000s	1157.830us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	2653.365us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	1135.714us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	1007.299us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	8.000s	487.691us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	5072.187us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	18.267us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	32.834us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	56.741us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	56.741us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	139.995us	1	1	100.00
	i2c_csr_rw	1.000s	162.013us	1	1	100.00
	i2c_csr_aliasing	3.000s	59.912us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	91.063us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	139.995us	1	1	100.00
	i2c_csr_rw	1.000s	162.013us	1	1	100.00
	i2c_csr_aliasing	3.000s	59.912us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	91.063us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	347.298us	1	1	100.00
	i2c_sec_cm	2.000s	252.363us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	347.298us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	4.000s	1056.294us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	462.847us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	2.000s	656.208us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	94971704072519410813502176420378550298639794914044995424434035599628811455493	89	UVM_INFO @ 96409757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	90477988740423551209018898039647368624697447776423533568280541016849820578233	103	UVM_INFO @ 315116241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	73699196828385573930940097741540173233207816098987116319488391236479744230628	93	UVM_INFO @ 1056293656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	31428541611946148712306782090797779299166042781861137290221660779487578884489	103	UVM_INFO @ 656208150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	23976049070820327258690675384160232282936641485102424684183340643012583477686	93	UVM_INFO @ 978273503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	67982486610163363193209806264176363104985512989879332860411412714460002535746	87	UVM_INFO @ 462847488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	i2c_target_stress_all	6216226747593181233935087689622729298590549527249179094883646287891153106099	None
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	43641438678492161380274833866268030814813672699039164998977469228542644362731	88	UVM_INFO @ 10083733442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)				1 test run
	i2c_host_mode_toggle	106159680928414063838867886893497843929870545354388665539407608054674688838269	88	UVM_INFO @ 23670995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---