Simulation Results: kmac/masked

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.84 %
  • code
  • 69.34 %
  • assert
  • 98.31 %
  • func
  • 77.87 %
  • line
  • 96.20 %
  • branch
  • 90.19 %
  • cond
  • 84.94 %
  • toggle
  • 29.17 %
  • FSM
  • 46.20 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 46.710s 6706.381us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.460s 60.590us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.180s 111.644us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 12.730s 2454.998us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.710s 1300.331us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.780s 33.721us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.180s 111.644us 1 1 100.00
kmac_csr_aliasing 5.710s 1300.331us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.000s 40.221us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.180s 57.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 426.900s 73856.942us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 812.910s 12558.153us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 37.650s 14397.604us 1 1 100.00
kmac_test_vectors_sha3_256 27.940s 1895.547us 1 1 100.00
kmac_test_vectors_sha3_384 20.160s 3886.889us 1 1 100.00
kmac_test_vectors_sha3_512 1110.080s 54365.474us 1 1 100.00
kmac_test_vectors_shake_128 211.920s 132742.055us 1 1 100.00
kmac_test_vectors_shake_256 291.090s 16743.610us 1 1 100.00
kmac_test_vectors_kmac 2.370s 313.336us 1 1 100.00
kmac_test_vectors_kmac_xof 2.100s 90.620us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 262.020s 24036.827us 1 1 100.00
app 0 1 0.00
kmac_app 10.510s 484.382us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 1.050s 328.150us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 3.420s 511.636us 0 1 0.00
error 0 1 0.00
kmac_error 144.560s 18576.661us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.350s 202.972us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.380s 182.449us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 1.180s 249.786us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 1.260s 22.046us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.120s 159.702us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.210s 38.526us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 2.220s 148.849us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.750s 24.250us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.950s 79.964us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.830s 71.962us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.830s 71.962us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.460s 60.590us 1 1 100.00
kmac_csr_rw 1.180s 111.644us 1 1 100.00
kmac_csr_aliasing 5.710s 1300.331us 1 1 100.00
kmac_same_csr_outstanding 1.970s 119.268us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.460s 60.590us 1 1 100.00
kmac_csr_rw 1.180s 111.644us 1 1 100.00
kmac_csr_aliasing 5.710s 1300.331us 1 1 100.00
kmac_same_csr_outstanding 1.970s 119.268us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.180s 84.085us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.180s 84.085us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.180s 84.085us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.180s 84.085us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.340s 50.215us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 73.300s 6277.620us 1 1 100.00
kmac_tl_intg_err 2.630s 141.017us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.630s 141.017us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.210s 38.526us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 46.710s 6706.381us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 262.020s 24036.827us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.180s 84.085us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 73.300s 6277.620us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 73.300s 6277.620us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 73.300s 6277.620us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 46.710s 6706.381us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.210s 38.526us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 73.300s 6277.620us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 8.500s 858.345us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 46.710s 6706.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 5.050s 333.742us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 7 test runs
kmac_app 33255437944305020145954242739501078272904441030691793011550683897318956829096 81
UVM_INFO @ 484381661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 18646652960055240726920703406452459309313301672246759036759963022096088179382 77
UVM_INFO @ 328149534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 76711640516432950673268131211422420330867273024919213984620187287299087647386 78
UVM_INFO @ 511636437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 43808235429143610144855871909558303338433962704803597603664931005614389735849 154
UVM_INFO @ 18576660923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 18296899105714535364474623399296184448219183359532396411584829956130770741047 77
UVM_INFO @ 159701930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 96048163237544840492132928470863939416378124769848546090429190104239906310227 80
UVM_INFO @ 148849492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 71395352822037300956379817604418474117621567565075340013843704228206384974408 95
UVM_INFO @ 333742396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_sideload_invalid 51393807469995133314372656507060995267033905698059585713331218656861555407910 81
UVM_ERROR @ 182448708 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 182448708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 86424595107781370206466437821626120364537868098466825956199787987426235863379 78
UVM_ERROR @ 202971880 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 202971880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 1 test run
kmac_mubi 19056474198669533010863076212376927425992678270759138487757629258517118792631 80
UVM_INFO @ 858344827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---