Simulation Results: kmac/unmasked

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.52 %
  • code
  • 66.75 %
  • assert
  • 95.62 %
  • func
  • 76.18 %
  • line
  • 92.91 %
  • branch
  • 87.43 %
  • cond
  • 85.15 %
  • toggle
  • 27.36 %
  • FSM
  • 40.88 %
Validation stages
V1
100.00%
V2
75.86%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 13.090s 6361.955us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.050s 14.639us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.140s 74.361us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 17.570s 1883.167us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.150s 2111.217us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.630s 370.325us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.140s 74.361us 1 1 100.00
kmac_csr_aliasing 7.150s 2111.217us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.860s 14.846us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.420s 121.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 820.950s 41168.673us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 317.950s 6140.373us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 2085.410s 102592.853us 1 1 100.00
kmac_test_vectors_sha3_256 1977.580s 217919.027us 1 1 100.00
kmac_test_vectors_sha3_384 1267.030s 289089.446us 1 1 100.00
kmac_test_vectors_sha3_512 884.880s 59062.126us 1 1 100.00
kmac_test_vectors_shake_128 130.710s 4788.462us 1 1 100.00
kmac_test_vectors_shake_256 286.990s 24978.424us 1 1 100.00
kmac_test_vectors_kmac 2.790s 556.937us 1 1 100.00
kmac_test_vectors_kmac_xof 2.060s 74.953us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 178.340s 24636.125us 1 1 100.00
app 0 1 0.00
kmac_app 1.330s 85.061us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 13.870s 4025.644us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 15.910s 10523.839us 0 1 0.00
error 1 1 100.00
kmac_error 39.360s 873.195us 1 1 100.00
key_error 0 1 0.00
kmac_key_error 1.240s 22.122us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.110s 36.295us 0 1 0.00
edn_timeout_error 0 1 0.00
kmac_edn_timeout_error 18.460s 4036.435us 0 1 0.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 24.620s 11671.160us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.120s 47.974us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.750s 60.166us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 144.270s 3312.321us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 1.190s 24.613us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.800s 66.004us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.830s 107.581us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.830s 107.581us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.050s 14.639us 1 1 100.00
kmac_csr_rw 1.140s 74.361us 1 1 100.00
kmac_csr_aliasing 7.150s 2111.217us 1 1 100.00
kmac_same_csr_outstanding 1.500s 26.232us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.050s 14.639us 1 1 100.00
kmac_csr_rw 1.140s 74.361us 1 1 100.00
kmac_csr_aliasing 7.150s 2111.217us 1 1 100.00
kmac_same_csr_outstanding 1.500s 26.232us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 2.510s 314.301us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 2.510s 314.301us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 2.510s 314.301us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 2.510s 314.301us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.830s 71.798us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 50.210s 23980.232us 1 1 100.00
kmac_tl_intg_err 3.440s 446.291us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.440s 446.291us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.750s 60.166us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 13.090s 6361.955us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 178.340s 24636.125us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 2.510s 314.301us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 50.210s 23980.232us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 50.210s 23980.232us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 50.210s 23980.232us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 13.090s 6361.955us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.750s 60.166us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 50.210s 23980.232us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 1.260s 47.133us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 13.090s 6361.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 38.350s 9945.205us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 5 test runs
kmac_sideload_invalid 42634422282897544985058549611636776168381822966925966298946103991054216023799 76
UVM_INFO @ 36295335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app 112062629304374082044341338922237344993352164236210987949527816373127890742499 77
UVM_INFO @ 85060591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 73664719212427655162621874233441106591737094413004302816446330951960769314245 86
UVM_INFO @ 4025644491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 106869899842733787636829192520283910841810674788850146868451778034444574001271 85
UVM_INFO @ 10523838700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 50618724968245660868504698649602893732737202322759069178105184525448634257162 77
UVM_INFO @ 47973501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_key_error 87342887207607580028967356389617268400412935506200232482951324433412481638025 78
UVM_ERROR @ 22122016 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 22122016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_edn_timeout_error 40580135513809912109205732291041837556197264982397734565634989528499769523954 87
UVM_ERROR @ 4036435482 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 4036435482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 1 test run
kmac_mubi 16248574387896001707197736117996892774765406154924601664041341714641597954972 77
UVM_INFO @ 47132884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 106591763899618904077881723174062516752732808922748642248507538958267348568671 143
UVM_INFO @ 9945205155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---