Simulation Results: lc_ctrl/volatile_unlock_disabled

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.83 %
  • code
  • 92.82 %
  • assert
  • 96.69 %
  • func
  • 85.99 %
  • block
  • 96.57 %
  • line
  • 97.26 %
  • branch
  • 91.26 %
  • toggle
  • 87.51 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 256.210us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 57.195us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 120.285us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 211.385us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 147.269us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 29.294us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 120.285us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 147.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 229.974us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 449.865us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 23.495us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 287.528us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 245.058us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 2125.007us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 245.058us 1 1 100.00
lc_ctrl_prog_failure 3.000s 287.528us 1 1 100.00
lc_ctrl_errors 5.000s 2125.007us 1 1 100.00
lc_ctrl_security_escalation 7.000s 1621.763us 1 1 100.00
lc_ctrl_jtag_state_failure 20.000s 6507.775us 1 1 100.00
lc_ctrl_jtag_prog_failure 10.000s 3640.515us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 1716.438us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 10.000s 979.070us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 378.726us 1 1 100.00
lc_ctrl_jtag_prog_failure 10.000s 3640.515us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 1716.438us 1 1 100.00
lc_ctrl_jtag_access 7.000s 1152.252us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 809.389us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 420.698us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 294.409us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.000s 8491.289us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 1648.511us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 313.802us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 307.119us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 45.902us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.000s 67.980us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.270us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 29.000s 112503.924us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 33.158us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 5.000s 499.146us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 5.000s 499.146us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 57.195us 1 1 100.00
lc_ctrl_csr_rw 2.000s 120.285us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 147.269us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 43.774us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 57.195us 1 1 100.00
lc_ctrl_csr_rw 2.000s 120.285us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 147.269us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 43.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 245.029us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 577.871us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 577.871us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 449.865us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 245.058us 1 1 100.00
lc_ctrl_sec_cm 3.000s 245.029us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 245.058us 1 1 100.00
lc_ctrl_sec_cm 3.000s 245.029us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 245.058us 1 1 100.00
lc_ctrl_sec_cm 3.000s 245.029us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 245.058us 1 1 100.00
lc_ctrl_sec_cm 3.000s 245.029us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 245.058us 1 1 100.00
lc_ctrl_sec_cm 3.000s 245.029us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 245.058us 1 1 100.00
lc_ctrl_sec_cm 3.000s 245.029us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 245.058us 1 1 100.00
lc_ctrl_sec_cm 3.000s 245.029us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 245.058us 1 1 100.00
lc_ctrl_sec_cm 3.000s 245.029us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.000s 1621.763us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 229.974us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 378.726us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.000s 1042.243us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.000s 1042.243us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 2191.326us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 807.865us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 807.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 52.000s 13220.568us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 29712111929992530852266148095854065158323197844632266287265617006601277789229 5865
UVM_INFO @ 13220568281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---