Simulation Results: lc_ctrl/volatile_unlock_enabled

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.14 %
  • code
  • 93.41 %
  • assert
  • 96.69 %
  • func
  • 86.31 %
  • block
  • 97.11 %
  • line
  • 97.66 %
  • branch
  • 92.68 %
  • toggle
  • 88.06 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 155.688us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 17.885us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.320us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 199.758us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 158.354us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 25.798us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 25.320us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 158.354us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 127.783us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 138.890us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.350us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 334.838us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 905.676us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 1700.867us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 905.676us 1 1 100.00
lc_ctrl_prog_failure 3.000s 334.838us 1 1 100.00
lc_ctrl_errors 6.000s 1700.867us 1 1 100.00
lc_ctrl_security_escalation 7.000s 556.053us 1 1 100.00
lc_ctrl_jtag_state_failure 22.000s 3461.161us 1 1 100.00
lc_ctrl_jtag_prog_failure 11.000s 2881.364us 1 1 100.00
lc_ctrl_jtag_errors 23.000s 3821.703us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 477.469us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 635.841us 1 1 100.00
lc_ctrl_jtag_prog_failure 11.000s 2881.364us 1 1 100.00
lc_ctrl_jtag_errors 23.000s 3821.703us 1 1 100.00
lc_ctrl_jtag_access 14.000s 3560.873us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.000s 2524.903us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 140.258us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 54.898us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 1207.799us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 410.622us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 499.490us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 585.586us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 48.753us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.000s 843.411us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 40.690us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 35.000s 10347.554us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 119.668us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 52.472us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 52.472us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 17.885us 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.320us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 158.354us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 169.952us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 17.885us 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.320us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 158.354us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 169.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 113.071us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 302.738us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 302.738us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 138.890us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 905.676us 1 1 100.00
lc_ctrl_sec_cm 2.000s 113.071us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 905.676us 1 1 100.00
lc_ctrl_sec_cm 2.000s 113.071us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 905.676us 1 1 100.00
lc_ctrl_sec_cm 2.000s 113.071us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 905.676us 1 1 100.00
lc_ctrl_sec_cm 2.000s 113.071us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 905.676us 1 1 100.00
lc_ctrl_sec_cm 2.000s 113.071us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 905.676us 1 1 100.00
lc_ctrl_sec_cm 2.000s 113.071us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 905.676us 1 1 100.00
lc_ctrl_sec_cm 2.000s 113.071us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 905.676us 1 1 100.00
lc_ctrl_sec_cm 2.000s 113.071us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.000s 556.053us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 127.783us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 635.841us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.000s 407.305us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.000s 407.305us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 417.854us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 241.117us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 241.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 15.000s 2492.113us 1 1 100.00