Simulation Results: otbn

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.88 %
  • code
  • 84.78 %
  • assert
  • 87.78 %
  • func
  • 94.07 %
  • block
  • 99.21 %
  • line
  • 99.41 %
  • branch
  • 94.42 %
  • toggle
  • 81.91 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 157.076us 1 1 100.00
single_binary 1 1 100.00
otbn_single 7.000s 89.355us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 26.481us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 41.609us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 8.000s 165.667us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 15.805us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 68.434us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 41.609us 1 1 100.00
otbn_csr_aliasing 4.000s 15.805us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 97.000s 2153.996us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 25.000s 1074.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 29.000s 359.204us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 54.000s 255.315us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 47.000s 415.285us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 105.000s 1310.427us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 51.612us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 50.856us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 14.000s 402.066us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 55.209us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 18.716us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 52.248us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 52.248us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 26.481us 1 1 100.00
otbn_csr_rw 3.000s 41.609us 1 1 100.00
otbn_csr_aliasing 4.000s 15.805us 1 1 100.00
otbn_same_csr_outstanding 4.000s 43.695us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 26.481us 1 1 100.00
otbn_csr_rw 3.000s 41.609us 1 1 100.00
otbn_csr_aliasing 4.000s 15.805us 1 1 100.00
otbn_same_csr_outstanding 4.000s 43.695us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 21.526us 1 1 100.00
otbn_dmem_err 9.000s 108.777us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 9.000s 580.793us 1 1 100.00
otbn_controller_ispr_rdata_err 24.000s 73.146us 1 1 100.00
otbn_mac_bignum_acc_err 12.000s 66.742us 1 1 100.00
otbn_urnd_err 8.000s 21.185us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 19.590us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 22.917us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 24.991us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
otbn_tl_intg_err 22.000s 597.571us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 47.000s 400.971us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 157.076us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 108.777us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 21.526us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 22.000s 597.571us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 51.612us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 21.526us 1 1 100.00
otbn_dmem_err 9.000s 108.777us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 50.856us 1 1 100.00
otbn_illegal_mem_acc 6.000s 19.590us 1 1 100.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 7.000s 89.355us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 21.526us 1 1 100.00
otbn_dmem_err 9.000s 108.777us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 50.856us 1 1 100.00
otbn_illegal_mem_acc 6.000s 19.590us 1 1 100.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 51.612us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 21.526us 1 1 100.00
otbn_dmem_err 9.000s 108.777us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 50.856us 1 1 100.00
otbn_illegal_mem_acc 6.000s 19.590us 1 1 100.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 7.000s 89.355us 1 1 100.00
sec_cm_ctrl_redun 0 1 0.00
otbn_ctrl_redun 6.000s 6.055us 0 1 0.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 143.534us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 44.000s 104.660us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 44.000s 104.660us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 35.085us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 61.900us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 50.054us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 50.054us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 17.167us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 89.355us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 89.355us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 7.000s 89.355us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 47.000s 415.285us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 7.000s 89.355us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 7.000s 89.355us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 55.006us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 7.000s 89.355us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 13.000s 45.850us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 243.000s 5969.827us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 72.697us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_ctrl_redun 66801892319933650760469928135422805885028007672107719343748322821585833241033 109
UVM_ERROR @ 6055091 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 6055091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 33357751114630556824026182813023031243318092139321233413284395665012149917456 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 50053537 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 50053537 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 50053537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 40657412669163897590283171351741687176025029355287927851149479612651992679580 212
UVM_INFO @ 5969826502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 4157856088504500312727238084188272046628507555782589943268996786652558311476 118
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 45849834 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 45849834 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 45849834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---