Simulation Results: otp_ctrl

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.44 %
  • code
  • 70.36 %
  • assert
  • 93.37 %
  • func
  • 50.59 %
  • line
  • 86.94 %
  • branch
  • 83.28 %
  • cond
  • 85.24 %
  • toggle
  • 62.86 %
  • FSM
  • 33.49 %
Validation stages
V1
100.00%
V2
55.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.290s 57.906us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.630s 268.500us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.530s 498.639us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.610s 88.722us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.530s 918.904us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 10.190s 849.961us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.870s 316.760us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.610s 88.722us 1 1 100.00
otp_ctrl_csr_aliasing 10.190s 849.961us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.180s 154.904us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.700s 118.072us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 101.680s 2903.900us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.430s 192.190us 0 1 0.00
partition_check 0 2 0.00
otp_ctrl_background_chks 12.530s 972.302us 0 1 0.00
otp_ctrl_check_fail 7.000s 2859.977us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.310s 267.292us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 15.490s 6861.539us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 11.800s 681.758us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 6.430s 270.977us 1 1 100.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 24.970s 3457.328us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 21.460s 1532.066us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 8.180s 4603.985us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 14.760s 4405.417us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.070s 184.544us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.840s 132.345us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.600s 87.700us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.600s 87.700us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.530s 498.639us 1 1 100.00
otp_ctrl_csr_rw 1.610s 88.722us 1 1 100.00
otp_ctrl_csr_aliasing 10.190s 849.961us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.250s 367.708us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.530s 498.639us 1 1 100.00
otp_ctrl_csr_rw 1.610s 88.722us 1 1 100.00
otp_ctrl_csr_aliasing 10.190s 849.961us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.250s 367.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
otp_ctrl_tl_intg_err 11.780s 1305.155us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.780s 1305.155us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.630s 268.500us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.630s 268.500us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_lci_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
sec_cm_kdi_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
otp_ctrl_macro_errs 21.460s 1532.066us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_lci_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
sec_cm_kdi_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
otp_ctrl_macro_errs 21.460s 1532.066us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.170s 43.996us 0 1 0.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.430s 192.190us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 7.000s 2859.977us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 15.490s 6861.539us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 15.490s 6861.539us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 15.490s 6861.539us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 15.490s 6861.539us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 15.490s 6861.539us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.630s 268.500us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 15.490s 6861.539us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.630s 268.500us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.620s 38758.047us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.310s 267.292us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.630s 268.500us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.630s 268.500us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 21.460s 1532.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 117.520s 69088.630us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 21.140s 548.446us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 3 test runs
otp_ctrl_background_chks 5008599718726402470319271462514840766578216581460850115280663316079858054253 16267
UVM_INFO @ 972302290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 43344968497163250666629982086127527358821937357101332963591140969265904135535 282
UVM_INFO @ 43995749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 87469651681255450713367995044011853046832205323352562759257082895385875800823 13340
UVM_INFO @ 681758138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_check_fail 4395882722133028641795050269753022346084832982815604018093353064310838946055 6165
UVM_INFO @ 2859977097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2510231290665884431171100250975432501334769127458407186596238771589896497634 19066
UVM_INFO @ 548445774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 58911104123875133302110327321099630468427215969124539598662650123073058344297 2143
UVM_INFO @ 4405416849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_partition_walk 71969441337230931860651061870040513045393411843919977408728479113159002161510 160055
UVM_INFO @ 2903900284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 83611808216274580593502307568575028774508496960051198786451471008157500695619 1491
UVM_INFO @ 192190246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_dai_lock 62655303197608154748996452436201528913290606527120312829104751955853636059649 17375
UVM_INFO @ 6861539448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 83912725902900726115271192543231438723387177526990575071773822636784328481004 8424
UVM_INFO @ 4603984532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 89166104445177873009380140312280494783564660688684006944688611240835635592898 89
UVM_INFO @ 69088629708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---