Simulation Results: rom_ctrl/32kb

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.43 %
  • code
  • 92.35 %
  • assert
  • 97.23 %
  • func
  • 96.71 %
  • block
  • 96.05 %
  • line
  • 96.47 %
  • branch
  • 93.55 %
  • toggle
  • 84.15 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 479.879us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 4483.052us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 163.180us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 677.224us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 1277.884us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 562.930us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 163.180us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 1277.884us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 155.772us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 173.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 176.999us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 6.000s 335.703us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 1082.272us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 299.625us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 692.067us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 692.067us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 4483.052us 1 1 100.00
rom_ctrl_csr_rw 3.000s 163.180us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 1277.884us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 137.250us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 4483.052us 1 1 100.00
rom_ctrl_csr_rw 3.000s 163.180us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 1277.884us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 137.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 4886.828us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 2039.382us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 98.000s 2768.981us 1 1 100.00
rom_ctrl_tl_intg_err 14.000s 1016.584us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 98.000s 2768.981us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 98.000s 2768.981us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 4886.828us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 4886.828us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 4886.828us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 4886.828us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 4886.828us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 98.000s 2768.981us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 98.000s 2768.981us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 479.879us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 479.879us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 479.879us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 14.000s 1016.584us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 4886.828us 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 1082.272us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 4886.828us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 4886.828us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 4886.828us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 2039.382us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 98.000s 2768.981us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 33.000s 1849.600us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 56661293438890558015510456404739549028490909681999846005405471733170645846248 88
UVM_INFO @ 176998841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---