Simulation Results: rom_ctrl/64kb

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.16 %
  • code
  • 91.00 %
  • assert
  • 97.53 %
  • func
  • 96.94 %
  • block
  • 95.74 %
  • line
  • 96.36 %
  • branch
  • 92.74 %
  • toggle
  • 84.40 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 301.737us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.000s 289.774us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.000s 1052.806us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 725.877us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 416.560us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.000s 562.120us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.000s 1052.806us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 416.560us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.000s 1025.424us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.000s 2511.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.000s 174.093us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 16.000s 2214.260us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 10.000s 1036.770us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.000s 334.516us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 365.060us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 365.060us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.000s 289.774us 1 1 100.00
rom_ctrl_csr_rw 6.000s 1052.806us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 416.560us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 788.832us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.000s 289.774us 1 1 100.00
rom_ctrl_csr_rw 6.000s 1052.806us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 416.560us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 788.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 5105.694us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.000s 735.936us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 206.000s 2456.651us 1 1 100.00
rom_ctrl_tl_intg_err 25.000s 936.328us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 206.000s 2456.651us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 206.000s 2456.651us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 5105.694us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 5105.694us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 5105.694us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 5105.694us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 5105.694us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 206.000s 2456.651us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 206.000s 2456.651us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 301.737us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 301.737us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 301.737us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 25.000s 936.328us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 5105.694us 1 1 100.00
rom_ctrl_kmac_err_chk 10.000s 1036.770us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 5105.694us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 5105.694us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 5105.694us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.000s 735.936us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 206.000s 2456.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 75.000s 3994.292us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 11167210533871362948178928521850273901610090588425923852964951490655673992860 88
UVM_INFO @ 174093398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---