Simulation Results: rstmgr

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.21 %
  • code
  • 99.30 %
  • assert
  • 98.35 %
  • func
  • 93.98 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.86 %
  • toggle
  • 99.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.260s 73.429us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.030s 93.856us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.940s 36.371us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.070s 81.550us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.550s 40.249us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.210s 99.409us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.940s 36.371us 1 1 100.00
rstmgr_csr_aliasing 1.550s 40.249us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.450s 148.537us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.060s 48.852us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.830s 39.860us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.330s 720.081us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.330s 720.081us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.330s 720.081us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.330s 720.081us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 10.250s 1501.559us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.910s 37.909us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.150s 46.692us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.150s 46.692us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.030s 93.856us 1 1 100.00
rstmgr_csr_rw 0.940s 36.371us 1 1 100.00
rstmgr_csr_aliasing 1.550s 40.249us 1 1 100.00
rstmgr_same_csr_outstanding 1.050s 39.897us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.030s 93.856us 1 1 100.00
rstmgr_csr_rw 0.940s 36.371us 1 1 100.00
rstmgr_csr_aliasing 1.550s 40.249us 1 1 100.00
rstmgr_same_csr_outstanding 1.050s 39.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 16.470s 3478.070us 1 1 100.00
rstmgr_tl_intg_err 2.600s 334.397us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 16.470s 3478.070us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 16.470s 3478.070us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.600s 334.397us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.210s 60.488us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.320s 417.641us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.280s 291.635us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 16.470s 3478.070us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.940s 36.371us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.940s 36.371us 1 1 100.00