Simulation Results

Simulation Results: rv_dm/use_dmi_interface

08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
90.83 %

code
81.82 %

assert
96.66 %

func
94.01 %

block
92.79 %

line
93.41 %

branch
80.43 %

toggle
73.09 %

FSM
80.36 %

Validation stages

V1		96.30%
V2		78.26%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	32.000s	1736.768us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	31.000s	888.423us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	34.000s	592.468us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	35.000s	19779.128us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	32.000s	434.948us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	33.000s	3701.341us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	32.000s	5728.708us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	49.000s	32905.758us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	146.000s	125835.676us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	565.155us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	30.000s	394.251us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	30.000s	216.114us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	33.000s	121.694us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	31.000s	144.724us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	33.000s	698.516us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	31.000s	241.283us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	32.000s	540.755us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	565.155us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	31.000s	136.719us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	34.000s	395.377us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	30.000s	216.114us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	32.000s	133.406us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	30.000s	90.675us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	32.000s	170.095us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	84.000s	50478.554us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	46.000s	2787.737us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	33.000s	114.593us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	46.000s	2787.737us	1	1	100.00
	rv_dm_csr_rw	32.000s	170.095us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	31.000s	60.518us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	33.000s	52.390us	1	1	100.00

18/23 passed

78.26 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	32.000s	1736.768us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	31.000s	586.353us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	32.000s	173.839us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	33.000s	124.155us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	31.000s	1792.396us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	38.000s	4240.575us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	31.000s	88.347us	0	1	0.00
bad_sba				1	1	100.00
	rv_dm_bad_sba_tl_access	46.000s	12682.935us	1	1	100.00
sba_autoincrement				1	1	100.00
	rv_dm_autoincr_sba_tl_access	43.000s	18538.371us	1	1	100.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	30.000s	188.112us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	37.000s	3137.183us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	32.000s	210.038us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	30.000s	62.230us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	33.000s	4546.674us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	47.000s	2625.628us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	35.000s	63.239us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	3618.000s	10000000.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	31.000s	38.172us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	242.802us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	242.802us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	46.000s	2787.737us	1	1	100.00
	rv_dm_csr_hw_reset	30.000s	90.675us	1	1	100.00
	rv_dm_csr_rw	32.000s	170.095us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	2232.739us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	46.000s	2787.737us	1	1	100.00
	rv_dm_csr_hw_reset	30.000s	90.675us	1	1	100.00
	rv_dm_csr_rw	32.000s	170.095us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	2232.739us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	34.000s	3036.588us	1	1	100.00
	rv_dm_tl_intg_err	37.000s	2474.877us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	37.000s	2474.877us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	37.000s	3137.183us	1	1	100.00
	rv_dm_debug_disabled	33.000s	33.190us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	37.000s	3137.183us	1	1	100.00
	rv_dm_debug_disabled	33.000s	33.190us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	32.000s	1736.768us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	31.000s	287.367us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	120.195us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	120.195us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	31.000s	287.367us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	50.000s	9817.995us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	504.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	83083344795031349381467693607084080975561054235949505363859800285721324757740	87	UVM_INFO @ 188111584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	66039718088848216430392231644933683476116287537324997505478126166743030823838	117	UVM_INFO @ 9817994528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	34628708303805461279890888310622849321012440164372679502137643349494097235809	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	9828273608684324386195402132375964071439595319552146491191327888998364188101	89	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				1 test run
	rv_dm_sba_tl_access	28385322409006283885541481142002410530898946116823277752917153092061381616300	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23825
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	11520749418919968759629364956350620113691859415040123799762297179839080165800	107	UVM_INFO @ 88346886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	72728105945119045292686495799796846728235799638316028843610600280516095642948	87	UVM_INFO @ 121694330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	46994868486859443970184860014972683500064431519798600257364452580810420602392	87	UVM_INFO @ 62230324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---