Simulation Results: rv_timer

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.50 %
  • code
  • 90.39 %
  • assert
  • 96.52 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 72.89 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 699.917us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 2.000s 12.939us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 11.665us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 159.417us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 161.042us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 25.646us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 11.665us 1 1 100.00
rv_timer_csr_aliasing 1.000s 161.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 8.000s 1817.547us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 3.000s 976.266us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 1.000s 37.727us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 1.000s 37.727us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.000s 2783.352us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 39.653us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 2.000s 27.136us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 58.009us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 58.009us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 2.000s 12.939us 1 1 100.00
rv_timer_csr_rw 1.000s 11.665us 1 1 100.00
rv_timer_csr_aliasing 1.000s 161.042us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 29.888us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 2.000s 12.939us 1 1 100.00
rv_timer_csr_rw 1.000s 11.665us 1 1 100.00
rv_timer_csr_aliasing 1.000s 161.042us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 29.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 176.950us 1 1 100.00
rv_timer_tl_intg_err 1.000s 55.431us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 55.431us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 1.000s 175.612us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 2.000s 475.223us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 12.000s 4192.180us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 68917272473584473035199683616657992223394298423570621845247350017167068621547 84
UVM_INFO @ 475222679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 101942675868743447048068740201478639102590392551386064945395093448017338854438 84
UVM_INFO @ 1817546682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---