Simulation Results: spi_device/1r1w

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.31 %
  • code
  • 88.81 %
  • assert
  • 95.40 %
  • func
  • 68.73 %
  • block
  • 98.35 %
  • line
  • 98.77 %
  • branch
  • 97.01 %
  • toggle
  • 69.87 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 34.000s 1451.578us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 14.295us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 83.967us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 31.000s 5187.364us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 12.000s 307.123us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 2473.394us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 83.967us 1 1 100.00
spi_device_csr_aliasing 12.000s 307.123us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 10.637us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 174.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 16.049us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 1.123us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 4.990us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 50.383us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 50.383us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 12.000s 8691.686us 1 1 100.00
spi_device_tpm_sts_read 2.000s 282.616us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 59.000s 54268.341us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 12.000s 1690.060us 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.000s 127.712us 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.000s 127.712us 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 13.000s 577.637us 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 13.000s 577.637us 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 13.000s 577.637us 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 13.000s 577.637us 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 13.000s 577.637us 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 17.000s 2119.619us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 36.000s 16895.503us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 36.000s 16895.503us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 36.000s 16895.503us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.000s 144.660us 1 1 100.00
spi_device_read_buffer_direct 19.000s 1721.189us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 36.000s 16895.503us 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 245.000s 130279.330us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 12.000s 9416.125us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 12.000s 9416.125us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 11.000s 861.251us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 34.000s 1451.578us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 152.000s 14921.041us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 656.000s 250068.767us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 34.731us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 20.357us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.000s 108.712us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.000s 108.712us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 14.295us 1 1 100.00
spi_device_csr_rw 2.000s 83.967us 1 1 100.00
spi_device_csr_aliasing 12.000s 307.123us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 116.976us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 14.295us 1 1 100.00
spi_device_csr_rw 2.000s 83.967us 1 1 100.00
spi_device_csr_aliasing 12.000s 307.123us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 116.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 143.845us 1 1 100.00
spi_device_tl_intg_err 9.000s 463.108us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.000s 463.108us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 88538163850241864154651593707379494308935427785088393776758092773856050419575 87
UVM_ERROR @ 847407 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1000] not found within the scope .
UVM_ERROR @ 847407 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1000] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 85619554413787675075849614854717995836981046834758513643615606080438334519184 85
UVM_ERROR @ 2662356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe720ad [111001110010000010101101] vs 0x0 [0])
UVM_ERROR @ 2740356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x27b12d [1001111011000100101101] vs 0x0 [0])
UVM_ERROR @ 2764356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbf2a2f [101111110010101000101111] vs 0x0 [0])
UVM_ERROR @ 2766356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb69b73 [101101101001101101110011] vs 0x0 [0])