Simulation Results: sram_ctrl/main

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.12 %
  • code
  • 95.67 %
  • assert
  • 98.10 %
  • func
  • 94.60 %
  • block
  • 96.03 %
  • line
  • 96.83 %
  • branch
  • 94.01 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 719.233us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 27.206us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.572us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 2042.131us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.228us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 667.997us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 17.572us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.228us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 222.000s 61746.498us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 54.000s 2686.216us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 1396.596us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 144.000s 34940.159us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 154.000s 28252.040us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 25.000s 6444.000us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 61.000s 69491.044us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 23.000s 35480.824us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 1681.778us 1 1 100.00
sram_ctrl_partial_access_b2b 129.000s 13214.406us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 665.082us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 678.679us 0 1 0.00
sram_ctrl_throughput_w_readback 5.000s 2654.438us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1182.538us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 344.303us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 47.000s 11531.388us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 38.966us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 146.656us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 146.656us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 27.206us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.572us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.228us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 37.063us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 27.206us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.572us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.228us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 37.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 7055.967us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 535.155us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 968.827us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 535.155us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 968.827us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1182.538us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1182.538us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.572us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 23.000s 35480.824us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 35480.824us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 35480.824us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 61.000s 69491.044us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 2772.063us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 7055.967us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 890.070us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 719.233us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 719.233us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 23.000s 35480.824us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 535.155us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 61.000s 69491.044us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 535.155us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 535.155us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 719.233us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 535.155us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.000s 4918.386us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 28401721702809064531030543375546741442428561523139692730574629633577955939452 86
UVM_INFO @ 665081542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 74558213954212614161642939184175520771230588117482392714411360022797007421048 86
UVM_INFO @ 678678583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 16340126681256829933407840288163268424365397518004204302661084909728566092328 86
UVM_INFO @ 2654437605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---