Simulation Results: sram_ctrl/ret

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.63 %
  • code
  • 81.55 %
  • assert
  • 97.94 %
  • func
  • 92.40 %
  • block
  • 92.75 %
  • line
  • 93.72 %
  • branch
  • 87.48 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 110.536us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 99.685us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.384us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 382.813us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.216us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 55.032us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 25.384us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.216us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.000s 241.953us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 6.000s 191.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 1805.207us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 91.000s 1856.444us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 581.802us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 6.000s 988.421us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 601.037us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 10.000s 483.586us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 88.270us 1 1 100.00
sram_ctrl_partial_access_b2b 146.000s 8035.941us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 50.796us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 100.492us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 28.510us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 254.976us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 28.461us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 29.000s 19407.774us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 24.881us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 277.155us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 277.155us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 99.685us 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.384us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.216us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 75.219us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 99.685us 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.384us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.216us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 75.219us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 488.569us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 2550.475us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 178.610us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 2550.475us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 178.610us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 254.976us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 254.976us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.384us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 10.000s 483.586us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 483.586us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 483.586us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 601.037us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 64.118us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 488.569us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 52.069us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 110.536us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 110.536us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 10.000s 483.586us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 2550.475us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 601.037us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 2550.475us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 2550.475us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 110.536us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 2550.475us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 25.000s 718.300us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 71435268107646022721061544648902901791328863211967939366352830410922101169016 86
UVM_INFO @ 50796273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 96815487006969609924947136992387631897411301570668457255432586572760629111913 86
UVM_INFO @ 100491715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 96913779907959203682612976662921117624087475298610890644797627197220854493942 86
UVM_INFO @ 28509556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---