Simulation Results: uart

 
08/07/2026 19:40:29 DVSim: v1.49.12 sha: 197a519 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.73 %
  • code
  • 92.53 %
  • assert
  • 97.98 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 653.266us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 19.492us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 15.079us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 651.201us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 39.131us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 62.228us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 15.079us 1 1 100.00
uart_csr_aliasing 1.000s 39.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 96.000s 88620.450us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 653.266us 1 1 100.00
uart_tx_rx 96.000s 88620.450us 1 1 100.00
parity_error 2 2 100.00
uart_intr 16.000s 36100.113us 1 1 100.00
uart_rx_parity_err 20.000s 114600.822us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 96.000s 88620.450us 1 1 100.00
uart_intr 16.000s 36100.113us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 21.000s 60440.470us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 13.000s 12038.505us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 11.000s 40097.112us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 16.000s 36100.113us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 16.000s 36100.113us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 16.000s 36100.113us 1 1 100.00
perf 1 1 100.00
uart_perf 52.000s 10340.707us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.000s 9905.171us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.000s 9905.171us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.000s 1443.532us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.000s 2078.653us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 1982.308us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 40.000s 7830.965us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 157.000s 123104.587us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 118.000s 412286.580us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 43.625us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 161.329us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 748.106us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 748.106us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 19.492us 1 1 100.00
uart_csr_rw 1.000s 15.079us 1 1 100.00
uart_csr_aliasing 1.000s 39.131us 1 1 100.00
uart_same_csr_outstanding 2.000s 57.535us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 19.492us 1 1 100.00
uart_csr_rw 1.000s 15.079us 1 1 100.00
uart_csr_aliasing 1.000s 39.131us 1 1 100.00
uart_same_csr_outstanding 2.000s 57.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 45.464us 1 1 100.00
uart_tl_intg_err 1.000s 315.862us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 315.862us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 11.000s 1270.664us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 33060520118153704709614514719335971535883989411948721584835600672823742108935 83
UVM_ERROR @ 201440130 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 201440130 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 253863836 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 253940760 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty