Simulation Results: ac_range_check

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.86 %
  • code
  • 93.03 %
  • assert
  • 97.75 %
  • func
  • 57.79 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 19.000s 460.701us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 39.000s 2292.176us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 141.400us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 192.199us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 33.000s 6658.176us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 12.000s 6847.507us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 1.000s 18.669us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 192.199us 1 1 100.00
ac_range_check_csr_aliasing 12.000s 6847.507us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 26.964us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 20.000s 548.561us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 143.000s 4601.418us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 48.801us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 50.150us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 71.779us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 71.779us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 141.400us 1 1 100.00
ac_range_check_csr_rw 2.000s 192.199us 1 1 100.00
ac_range_check_csr_aliasing 12.000s 6847.507us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 214.687us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 141.400us 1 1 100.00
ac_range_check_csr_rw 2.000s 192.199us 1 1 100.00
ac_range_check_csr_aliasing 12.000s 6847.507us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 214.687us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 2018.351us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 2018.351us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 2018.351us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 2018.351us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 56.000s 5605.158us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 12.922us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 344.435us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 218.000s 5251.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 29.000s 1598.497us 1 1 100.00