Simulation Results: aes/gcm_masked

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.29 %
  • code
  • 95.29 %
  • assert
  • 98.29 %
  • func
  • 65.29 %
  • block
  • 95.75 %
  • line
  • 97.51 %
  • branch
  • 89.46 %
  • toggle
  • 98.05 %
  • FSM
  • 96.13 %
Validation stages
V1
100.00%
V2
100.00%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 98.601us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 92.418us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 110.655us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 393.727us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 1006.436us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 122.604us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 60.290us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 393.727us 1 1 100.00
aes_csr_aliasing 2.000s 122.604us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 92.418us 1 1 100.00
aes_config_error 3.000s 86.248us 1 1 100.00
aes_stress 4.000s 194.305us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 92.418us 1 1 100.00
aes_config_error 3.000s 86.248us 1 1 100.00
aes_stress 4.000s 194.305us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 194.305us 1 1 100.00
aes_b2b 6.000s 176.810us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 194.305us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 92.418us 1 1 100.00
aes_config_error 3.000s 86.248us 1 1 100.00
aes_stress 4.000s 194.305us 1 1 100.00
aes_alert_reset 2.000s 72.516us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 81.357us 1 1 100.00
aes_config_error 3.000s 86.248us 1 1 100.00
aes_alert_reset 2.000s 72.516us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 113.003us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 1257.880us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 395.273us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 72.516us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 194.305us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 194.305us 1 1 100.00
aes_sideload 3.000s 142.153us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 9.000s 1792.123us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 24.000s 4784.473us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 195.564us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 140.787us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 121.543us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 121.543us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 110.655us 1 1 100.00
aes_csr_rw 2.000s 393.727us 1 1 100.00
aes_csr_aliasing 2.000s 122.604us 1 1 100.00
aes_same_csr_outstanding 2.000s 125.539us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 110.655us 1 1 100.00
aes_csr_rw 2.000s 393.727us 1 1 100.00
aes_csr_aliasing 2.000s 122.604us 1 1 100.00
aes_same_csr_outstanding 2.000s 125.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 240.533us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 4.000s 463.695us 0 1 0.00
aes_control_fi 2.000s 97.971us 1 1 100.00
aes_cipher_fi 3.000s 108.817us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 220.108us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 220.108us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 220.108us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 220.108us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 286.737us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 823.251us 1 1 100.00
aes_tl_intg_err 2.000s 166.402us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 166.402us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 72.516us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 220.108us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 220.108us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 92.418us 1 1 100.00
aes_stress 4.000s 194.305us 1 1 100.00
aes_alert_reset 2.000s 72.516us 1 1 100.00
aes_core_fi 2.000s 111.525us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 195.564us 1 1 100.00
aes_config_error 3.000s 86.248us 1 1 100.00
aes_stress 4.000s 194.305us 1 1 100.00
aes_core_fi 2.000s 111.525us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 220.108us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 54.081us 1 1 100.00
aes_stress 4.000s 194.305us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 194.305us 1 1 100.00
aes_sideload 3.000s 142.153us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 54.081us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 54.081us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 54.081us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 54.081us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 54.081us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 194.305us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 194.305us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 463.695us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 463.695us 0 1 0.00
aes_control_fi 2.000s 97.971us 1 1 100.00
aes_cipher_fi 3.000s 108.817us 1 1 100.00
aes_ctr_fi 2.000s 56.801us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 463.695us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 463.695us 0 1 0.00
aes_control_fi 2.000s 97.971us 1 1 100.00
aes_cipher_fi 3.000s 108.817us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 108.817us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 463.695us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 463.695us 0 1 0.00
aes_control_fi 2.000s 97.971us 1 1 100.00
aes_ctr_fi 2.000s 56.801us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 463.695us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 463.695us 0 1 0.00
aes_control_fi 2.000s 97.971us 1 1 100.00
aes_cipher_fi 3.000s 108.817us 1 1 100.00
aes_ctr_fi 2.000s 56.801us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 72.516us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 463.695us 0 1 0.00
aes_control_fi 2.000s 97.971us 1 1 100.00
aes_cipher_fi 3.000s 108.817us 1 1 100.00
aes_ctr_fi 2.000s 56.801us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 463.695us 0 1 0.00
aes_control_fi 2.000s 97.971us 1 1 100.00
aes_cipher_fi 3.000s 108.817us 1 1 100.00
aes_ctr_fi 2.000s 56.801us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 463.695us 0 1 0.00
aes_control_fi 2.000s 97.971us 1 1 100.00
aes_ctr_fi 2.000s 56.801us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 56.371us 1 1 100.00
aes_fi 4.000s 463.695us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 463.695us 0 1 0.00
aes_control_fi 2.000s 97.971us 1 1 100.00
aes_cipher_fi 3.000s 108.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 6.735us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 98449622722496628516878432858604009428897632707786878922831057452718236134369 11663
UVM_INFO @ 240532504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 1427216757166970963660025953495868885105299263332649567218797299705405473085 5175
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 51631941774963962314525317105777084816079626187352372521968266476792935329513 112
UVM_INFO @ 6735166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---