Simulation Results: aes/gcm_unmasked

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.89 %
  • code
  • 91.27 %
  • assert
  • 97.75 %
  • func
  • 62.65 %
  • block
  • 91.76 %
  • line
  • 93.12 %
  • branch
  • 85.32 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
88.24%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 58.120us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 233.892us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 60.145us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 63.649us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 1650.482us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 228.852us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 64.003us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 63.649us 1 1 100.00
aes_csr_aliasing 2.000s 228.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 233.892us 1 1 100.00
aes_config_error 2.000s 126.050us 1 1 100.00
aes_stress 2.000s 83.152us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 233.892us 1 1 100.00
aes_config_error 2.000s 126.050us 1 1 100.00
aes_stress 2.000s 83.152us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 83.152us 1 1 100.00
aes_b2b 5.000s 242.383us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 83.152us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 233.892us 1 1 100.00
aes_config_error 2.000s 126.050us 1 1 100.00
aes_stress 2.000s 83.152us 1 1 100.00
aes_alert_reset 2241.000s 200000.000us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 63.221us 1 1 100.00
aes_config_error 2.000s 126.050us 1 1 100.00
aes_alert_reset 2241.000s 200000.000us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 147.605us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 131.962us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 2241.000s 200000.000us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 83.152us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 83.152us 1 1 100.00
aes_sideload 2.000s 95.090us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 89.689us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.119s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 140.385us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 194.373us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 194.373us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 60.145us 1 1 100.00
aes_csr_rw 1.000s 63.649us 1 1 100.00
aes_csr_aliasing 2.000s 228.852us 1 1 100.00
aes_same_csr_outstanding 2.000s 124.813us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 60.145us 1 1 100.00
aes_csr_rw 1.000s 63.649us 1 1 100.00
aes_csr_aliasing 2.000s 228.852us 1 1 100.00
aes_same_csr_outstanding 2.000s 124.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 277.913us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 164.843us 0 1 0.00
aes_control_fi 2.000s 69.773us 1 1 100.00
aes_cipher_fi 1.000s 46.125us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 266.239us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 266.239us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 266.239us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 266.239us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 800.004us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1627.115us 1 1 100.00
aes_tl_intg_err 2.000s 283.320us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 283.320us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 2241.000s 200000.000us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 266.239us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 266.239us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 233.892us 1 1 100.00
aes_stress 2.000s 83.152us 1 1 100.00
aes_alert_reset 2241.000s 200000.000us 0 1 0.00
aes_core_fi 2.000s 67.020us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 126.050us 1 1 100.00
aes_stress 2.000s 83.152us 1 1 100.00
aes_core_fi 2.000s 67.020us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 266.239us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 71.956us 1 1 100.00
aes_stress 2.000s 83.152us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 83.152us 1 1 100.00
aes_sideload 2.000s 95.090us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 71.956us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 71.956us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 71.956us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 71.956us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 71.956us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 83.152us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 83.152us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 164.843us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 164.843us 0 1 0.00
aes_control_fi 2.000s 69.773us 1 1 100.00
aes_cipher_fi 1.000s 46.125us 1 1 100.00
aes_ctr_fi 2.000s 53.945us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 164.843us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 164.843us 0 1 0.00
aes_control_fi 2.000s 69.773us 1 1 100.00
aes_cipher_fi 1.000s 46.125us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 46.125us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 164.843us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 164.843us 0 1 0.00
aes_control_fi 2.000s 69.773us 1 1 100.00
aes_ctr_fi 2.000s 53.945us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 164.843us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 164.843us 0 1 0.00
aes_control_fi 2.000s 69.773us 1 1 100.00
aes_cipher_fi 1.000s 46.125us 1 1 100.00
aes_ctr_fi 2.000s 53.945us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 2241.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 164.843us 0 1 0.00
aes_control_fi 2.000s 69.773us 1 1 100.00
aes_cipher_fi 1.000s 46.125us 1 1 100.00
aes_ctr_fi 2.000s 53.945us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 164.843us 0 1 0.00
aes_control_fi 2.000s 69.773us 1 1 100.00
aes_cipher_fi 1.000s 46.125us 1 1 100.00
aes_ctr_fi 2.000s 53.945us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 164.843us 0 1 0.00
aes_control_fi 2.000s 69.773us 1 1 100.00
aes_ctr_fi 2.000s 53.945us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 164.843us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 164.843us 0 1 0.00
aes_control_fi 2.000s 69.773us 1 1 100.00
aes_cipher_fi 1.000s 46.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 590.795us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_alert_reset 60167761999188463624628663229587398420518448645086477629844977901191418147305 29332231
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 54581984524515077244120251946826316011144325680047640260038212047083164961427 6583
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_stress_all 78684954499083649569535368302133080522118168866402508421778722624612465514233 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 20038326954225794074242719152337452367441338137457107282781566068012701482846 161
UVM_INFO @ 590794541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---