Simulation Results: alert_handler

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.13 %
  • code
  • 90.77 %
  • assert
  • 98.02 %
  • func
  • 81.59 %
  • line
  • 99.70 %
  • branch
  • 98.39 %
  • cond
  • 91.46 %
  • toggle
  • 90.11 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 53.710s 3564.625us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.380s 24.473us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.900s 80.342us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 230.270s 6278.199us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 99.690s 2078.238us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.810s 117.615us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.900s 80.342us 1 1 100.00
alert_handler_csr_aliasing 99.690s 2078.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 115.170s 6066.142us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 22.390s 915.656us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 592.070s 9429.607us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 21.060s 2032.857us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 53.710s 3564.625us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 59.090s 1532.495us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 19.330s 471.294us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 91.220s 35411.506us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1380.170s 339481.122us 1 1 100.00
alert_handler_lpg_stub_clk 1643.370s 225935.754us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2998.120s 153776.828us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 8.980s 503.276us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.430s 145.215us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.310s 51.505us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 8.600s 91.003us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 8.600s 91.003us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.380s 24.473us 1 1 100.00
alert_handler_csr_rw 3.900s 80.342us 1 1 100.00
alert_handler_csr_aliasing 99.690s 2078.238us 1 1 100.00
alert_handler_same_csr_outstanding 19.440s 363.490us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.380s 24.473us 1 1 100.00
alert_handler_csr_rw 3.900s 80.342us 1 1 100.00
alert_handler_csr_aliasing 99.690s 2078.238us 1 1 100.00
alert_handler_same_csr_outstanding 19.440s 363.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 120.280s 2712.806us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 120.280s 2712.806us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 120.280s 2712.806us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 120.280s 2712.806us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 476.360s 5094.610us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 12.210s 4726.209us 1 1 100.00
alert_handler_tl_intg_err 62.920s 2615.188us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 62.920s 2615.188us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 120.280s 2712.806us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 53.710s 3564.625us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 53.710s 3564.625us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 53.710s 3564.625us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 53.710s 3564.625us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 21.060s 2032.857us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1380.170s 339481.122us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 21.060s 2032.857us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 592.070s 9429.607us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 592.070s 9429.607us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 12.210s 4726.209us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 12.210s 4726.209us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 12.210s 4726.209us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 12.210s 4726.209us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 12.210s 4726.209us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 12.210s 4726.209us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 12.210s 4726.209us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 12.210s 4726.209us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 12.210s 4726.209us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 32.090s 2665.025us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 72623956126669613029980231101817467417004582344534239405396473184373612414953 180
UVM_INFO @ 503275684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 108843750922764427935224637960261268852103861960943647051909413041725968449118 90
UVM_INFO @ 2665025287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---