Simulation Results: clkmgr

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.79 %
  • code
  • 68.48 %
  • assert
  • 89.46 %
  • func
  • 60.43 %
  • line
  • 81.61 %
  • branch
  • 86.53 %
  • cond
  • 77.82 %
  • toggle
  • 96.42 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.040s 19.134us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.960s 44.925us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.630s 1.779us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.380s 31.573us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.630s 122.363us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.830s 13.414us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.630s 1.779us 0 1 0.00
clkmgr_csr_aliasing 1.630s 122.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.880s 32.993us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.120s 49.575us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.880s 16.676us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.040s 19.134us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.780s 8.309us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.710s 5.887us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.780s 8.309us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.700s 3.994us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.910s 32.876us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.030s 44.279us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.030s 44.279us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.960s 44.925us 1 1 100.00
clkmgr_csr_rw 0.630s 1.779us 0 1 0.00
clkmgr_csr_aliasing 1.630s 122.363us 1 1 100.00
clkmgr_same_csr_outstanding 0.760s 12.066us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.960s 44.925us 1 1 100.00
clkmgr_csr_rw 0.630s 1.779us 0 1 0.00
clkmgr_csr_aliasing 1.630s 122.363us 1 1 100.00
clkmgr_same_csr_outstanding 0.760s 12.066us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.110s 45.957us 0 1 0.00
clkmgr_tl_intg_err 0.630s 3.383us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.970s 148.080us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.970s 148.080us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.970s 148.080us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.970s 148.080us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.890s 6.932us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.630s 3.383us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.780s 8.309us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.710s 5.887us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.970s 148.080us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 3.270s 288.153us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.630s 1.779us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.110s 45.957us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.630s 1.779us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.630s 1.779us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.110s 45.957us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.730s 3.912us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.880s 17.945us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_tl_intg_err 33192859079043633978230692423839354909127300580741615024496103032017925972528 75
UVM_INFO @ 3383451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 24942869050474594921882272705221462324234377051262872110775096809026658764299 75
UVM_INFO @ 1778719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 67504222566145511441046829393769995132851495697557171017449371894844682612103 76
UVM_INFO @ 13413868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 21708002585795415840183551967254147751449460218656804133816846682343058686271 77
UVM_INFO @ 8308523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 71900053016469104707139046836015928902033640579780495547209503126871033573257 77
UVM_INFO @ 17944563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 63305544147005246763075657896905984035170643968761422879522041375745587391624 77
UVM_INFO @ 5887470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 75670646272878676535547485403333164742683888225104526812969080147510636046498 77
UVM_INFO @ 3994083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 80721835610588478716181724355808787102463686933473394021338371939671389680802 74
UVM_INFO @ 3911728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 39006016521713532782356688266388778154988482876072912434208802068092308141862 75
UVM_INFO @ 6931652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 19157784894595379747881817181093447084432338042030056426722590629818855805885 100
UVM_INFO @ 45957321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 20380954528154692499411956717771819416935970902460542293339903683889890858204 75
UVM_INFO @ 31573288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 941572843888356082762538797564010597168320112060140902348567673955354366976 75
UVM_INFO @ 12066127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---