Simulation Results: csrng

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.60 %
  • code
  • 92.21 %
  • assert
  • 94.32 %
  • func
  • 73.27 %
  • block
  • 96.85 %
  • line
  • 97.62 %
  • branch
  • 92.26 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 1.000s 18.487us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 19.442us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 44.032us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 18.000s 581.688us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 96.394us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 14.889us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 44.032us 1 1 100.00
csrng_csr_aliasing 3.000s 96.394us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
alerts 1 1 100.00
csrng_alert 13.000s 523.354us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 24.546us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 24.546us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 78.000s 4471.562us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 41.728us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 56.420us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 7.000s 155.713us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 7.000s 155.713us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 19.442us 1 1 100.00
csrng_csr_rw 1.000s 44.032us 1 1 100.00
csrng_csr_aliasing 3.000s 96.394us 1 1 100.00
csrng_same_csr_outstanding 2.000s 39.704us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 19.442us 1 1 100.00
csrng_csr_rw 1.000s 44.032us 1 1 100.00
csrng_csr_aliasing 3.000s 96.394us 1 1 100.00
csrng_same_csr_outstanding 2.000s 39.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 152.800us 1 1 100.00
csrng_tl_intg_err 7.000s 348.112us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 6.487us 0 1 0.00
csrng_csr_rw 1.000s 44.032us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 13.000s 523.354us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 78.000s 4471.562us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
csrng_sec_cm 3.000s 152.800us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
csrng_sec_cm 3.000s 152.800us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
csrng_sec_cm 3.000s 152.800us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
csrng_sec_cm 3.000s 152.800us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
csrng_sec_cm 3.000s 152.800us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 13.000s 523.354us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 78.000s 4471.562us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 13.000s 523.354us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 7.000s 348.112us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
csrng_sec_cm 3.000s 152.800us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
csrng_sec_cm 3.000s 152.800us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 50.469us 1 1 100.00
csrng_err 2.000s 36.077us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.075s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 9864647755191736916195244091885422388684014404323488101939363363887096303403 100
UVM_INFO @ 24545833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 36391616078543685378750517595828105663214582186494482103889303521733371091243 99
UVM_INFO @ 6487335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 87541572630101085199339861310778608701415418100001759502693773922882092249807 None