Simulation Results: dma

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.77 %
  • code
  • 90.38 %
  • assert
  • 96.61 %
  • func
  • 61.31 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1096.542us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 3227.240us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 336.854us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 60.182us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 13.601us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 11.000s 1760.112us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 166.566us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 26.931us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 13.601us 1 1 100.00
dma_csr_aliasing 3.000s 166.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 67.000s 15452.639us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 51.000s 19113.827us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 723.000s 121225.574us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 723.000s 121225.574us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 51.000s 19113.827us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 83.000s 16879.860us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 723.000s 121225.574us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 3.000s 1265.378us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 141.000s 14833.791us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 15.190us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 46.842us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 32.166us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 32.166us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 60.182us 1 1 100.00
dma_csr_rw 2.000s 13.601us 1 1 100.00
dma_csr_aliasing 3.000s 166.566us 1 1 100.00
dma_same_csr_outstanding 2.000s 108.661us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 60.182us 1 1 100.00
dma_csr_rw 2.000s 13.601us 1 1 100.00
dma_csr_aliasing 3.000s 166.566us 1 1 100.00
dma_same_csr_outstanding 2.000s 108.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 1121.628us 1 1 100.00
dma_generic_stress 83.000s 16879.860us 1 1 100.00
dma_handshake_stress 723.000s 121225.574us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 1014.664us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 225.896us 1 1 100.00
dma_sec_cm 1.000s 35.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 148.000s 37762.008us 1 1 100.00
dma_longer_transfer 3.000s 474.444us 1 1 100.00
dma_stress_all_with_rand_reset 11.000s 2583.787us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 94620209184125981284973247390555947627694260736677309084062608681356682372381 113
UVM_INFO @ 2583786916ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---