Simulation Results: edn/edn0

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 78.68 %
  • code
  • 88.24 %
  • assert
  • 96.46 %
  • func
  • 51.33 %
  • block
  • 95.08 %
  • line
  • 97.61 %
  • branch
  • 89.26 %
  • toggle
  • 76.94 %
  • FSM
  • 89.15 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 17.742us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 145.317us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 45.395us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 167.759us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 142.568us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 138.103us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 45.395us 1 1 100.00
edn_csr_aliasing 2.000s 142.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 102.679us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 102.679us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 102.679us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 45.576us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 45.935us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 66.125us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 17.030us 1 1 100.00
edn_disable_auto_req_mode 2.000s 45.870us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 426.870us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 74.696us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 72.944us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.000s 207.868us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.000s 207.868us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 145.317us 1 1 100.00
edn_csr_rw 1.000s 45.395us 1 1 100.00
edn_csr_aliasing 2.000s 142.568us 1 1 100.00
edn_same_csr_outstanding 2.000s 29.629us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 145.317us 1 1 100.00
edn_csr_rw 1.000s 45.395us 1 1 100.00
edn_csr_aliasing 2.000s 142.568us 1 1 100.00
edn_same_csr_outstanding 2.000s 29.629us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.000s 1944.651us 1 1 100.00
edn_tl_intg_err 2.000s 714.964us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 19.683us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 45.935us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 1944.651us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 1944.651us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 1944.651us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 1944.651us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 45.935us 1 1 100.00
edn_sec_cm 7.000s 1944.651us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 45.935us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 714.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 51.000s 27414.044us 1 1 100.00