Simulation Results: edn/edn1

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.11 %
  • code
  • 82.90 %
  • assert
  • 98.18 %
  • func
  • 80.25 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 88.77 %
  • toggle
  • 86.33 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.790s 41.014us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.100s 50.513us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.820s 29.436us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.890s 81.975us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.300s 128.439us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.020s 26.766us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.820s 29.436us 1 1 100.00
edn_csr_aliasing 1.300s 128.439us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.310s 40.741us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.310s 40.741us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.310s 40.741us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.920s 25.354us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.280s 45.725us 1 1 100.00
errs 1 1 100.00
edn_err 0.870s 30.068us 1 1 100.00
disable 2 2 100.00
edn_disable 0.800s 13.728us 1 1 100.00
edn_disable_auto_req_mode 1.310s 44.083us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.750s 1627.548us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.920s 59.356us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.900s 70.466us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.240s 97.114us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.240s 97.114us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.100s 50.513us 1 1 100.00
edn_csr_rw 0.820s 29.436us 1 1 100.00
edn_csr_aliasing 1.300s 128.439us 1 1 100.00
edn_same_csr_outstanding 0.960s 63.078us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.100s 50.513us 1 1 100.00
edn_csr_rw 0.820s 29.436us 1 1 100.00
edn_csr_aliasing 1.300s 128.439us 1 1 100.00
edn_same_csr_outstanding 0.960s 63.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.080s 371.008us 1 1 100.00
edn_tl_intg_err 2.070s 262.353us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 70.214us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.280s 45.725us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.080s 371.008us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.080s 371.008us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.080s 371.008us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.080s 371.008us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.280s 45.725us 1 1 100.00
edn_sec_cm 4.080s 371.008us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.280s 45.725us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.070s 262.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 36.390s 2415.804us 1 1 100.00