Simulation Results: entropy_src/rng_16bits

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 70.36 %
  • code
  • 83.08 %
  • assert
  • 73.50 %
  • func
  • 54.49 %
  • block
  • 94.15 %
  • line
  • 97.82 %
  • branch
  • 86.18 %
  • toggle
  • 52.50 %
  • FSM
  • 95.83 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 28.446us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 30.420us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 112.134us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 14.000s 809.156us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 103.439us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 11.627us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 112.134us 1 1 100.00
entropy_src_csr_aliasing 3.000s 103.439us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 28.446us 1 1 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
entropy_src_fw_ov 148.000s 13039.585us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 148.000s 13039.585us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 394.000s 13049.041us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
entropy_src_intr 20.000s 15935.576us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
entropy_src_functional_alerts 5.000s 168.312us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 321.000s 14273.411us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 31.266us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 12.000s 478.941us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 24.288us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 18.411us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 5.000s 541.685us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 5.000s 541.685us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 30.420us 1 1 100.00
entropy_src_csr_rw 2.000s 112.134us 1 1 100.00
entropy_src_csr_aliasing 3.000s 103.439us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 31.881us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 30.420us 1 1 100.00
entropy_src_csr_rw 2.000s 112.134us 1 1 100.00
entropy_src_csr_aliasing 3.000s 103.439us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 31.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 57.565us 1 1 100.00
entropy_src_tl_intg_err 3.000s 102.261us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
entropy_src_cfg_regwen 1.000s 64.628us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
entropy_src_fw_ov 148.000s 13039.585us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 31.266us 1 1 100.00
entropy_src_sec_cm 3.000s 57.565us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 31.266us 1 1 100.00
entropy_src_sec_cm 3.000s 57.565us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 82.000s 14103.944us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 31.266us 1 1 100.00
entropy_src_sec_cm 3.000s 57.565us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 31.266us 1 1 100.00
entropy_src_sec_cm 3.000s 57.565us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 31.266us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 168.312us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 102.261us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 63.000s 14245.804us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 3.000s 116.887us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 28426908641175898233736640288016585234144317559263679248265224845980677932074 164
UVM_INFO @ 116886661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 84009630950156761167515246321381715913848775244812882658313483419530434077731 113
UVM_INFO @ 11627396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---