Simulation Results: hmac

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.04 %
  • code
  • 95.67 %
  • assert
  • 97.17 %
  • func
  • 29.28 %
  • block
  • 97.09 %
  • line
  • 98.21 %
  • branch
  • 92.70 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 12.000s 4554.913us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 124.026us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 55.997us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.000s 1697.026us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 204.757us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 38.825us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 55.997us 1 1 100.00
hmac_csr_aliasing 3.000s 204.757us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 76.000s 9377.267us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 6.000s 171.159us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 217.000s 8692.831us 1 1 100.00
hmac_test_sha384_vectors 411.000s 33158.840us 1 1 100.00
hmac_test_sha512_vectors 533.000s 21433.805us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 660.603us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 487.606us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 390.424us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 3.000s 258.410us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 64.000s 3563.093us 1 1 100.00
error 1 1 100.00
hmac_error 78.000s 7869.463us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 5.000s 135.537us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 12.000s 4554.913us 1 1 100.00
hmac_long_msg 76.000s 9377.267us 1 1 100.00
hmac_back_pressure 6.000s 171.159us 1 1 100.00
hmac_datapath_stress 64.000s 3563.093us 1 1 100.00
hmac_burst_wr 3.000s 258.410us 1 1 100.00
hmac_stress_all 175.000s 143898.000us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 12.000s 4554.913us 1 1 100.00
hmac_long_msg 76.000s 9377.267us 1 1 100.00
hmac_back_pressure 6.000s 171.159us 1 1 100.00
hmac_datapath_stress 64.000s 3563.093us 1 1 100.00
hmac_wipe_secret 5.000s 135.537us 1 1 100.00
hmac_test_sha256_vectors 217.000s 8692.831us 1 1 100.00
hmac_test_sha384_vectors 411.000s 33158.840us 1 1 100.00
hmac_test_sha512_vectors 533.000s 21433.805us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 660.603us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 487.606us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 390.424us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 12.000s 4554.913us 1 1 100.00
hmac_long_msg 76.000s 9377.267us 1 1 100.00
hmac_back_pressure 6.000s 171.159us 1 1 100.00
hmac_datapath_stress 64.000s 3563.093us 1 1 100.00
hmac_burst_wr 3.000s 258.410us 1 1 100.00
hmac_error 78.000s 7869.463us 1 1 100.00
hmac_wipe_secret 5.000s 135.537us 1 1 100.00
hmac_test_sha256_vectors 217.000s 8692.831us 1 1 100.00
hmac_test_sha384_vectors 411.000s 33158.840us 1 1 100.00
hmac_test_sha512_vectors 533.000s 21433.805us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 660.603us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 487.606us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 390.424us 1 1 100.00
hmac_stress_all 175.000s 143898.000us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 175.000s 143898.000us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 12.297us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 16.232us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 452.335us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 452.335us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 124.026us 1 1 100.00
hmac_csr_rw 1.000s 55.997us 1 1 100.00
hmac_csr_aliasing 3.000s 204.757us 1 1 100.00
hmac_same_csr_outstanding 2.000s 387.831us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 124.026us 1 1 100.00
hmac_csr_rw 1.000s 55.997us 1 1 100.00
hmac_csr_aliasing 3.000s 204.757us 1 1 100.00
hmac_same_csr_outstanding 2.000s 387.831us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 49.785us 1 1 100.00
hmac_tl_intg_err 3.000s 383.659us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 383.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 12.000s 4554.913us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 6.000s 105.810us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 21.000s 1401.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 29.454us 1 1 100.00