Simulation Results: i2c

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.59 %
  • code
  • 85.65 %
  • assert
  • 97.04 %
  • func
  • 80.07 %
  • block
  • 95.95 %
  • line
  • 95.37 %
  • branch
  • 92.74 %
  • toggle
  • 72.47 %
  • FSM
  • 82.01 %
Validation stages
V1
100.00%
V2
87.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 144.000s 2795.010us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 9.000s 1606.542us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 1.000s 25.502us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 1.000s 36.492us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.000s 157.624us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 3.000s 419.866us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 2.000s 145.382us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 1.000s 36.492us 1 1 100.00
i2c_csr_aliasing 3.000s 419.866us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 4.000s 184.044us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 3601.000s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 28.000s 4455.996us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 1.000s 26.567us 1 1 100.00
host_fifo_watermark 0 1 0.00
i2c_host_fifo_watermark 3600.000s 0.000us 0 1 0.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 902.000s 2146.764us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 2.000s 459.663us 1 1 100.00
i2c_host_fifo_fmt_empty 15.000s 331.748us 1 1 100.00
i2c_host_fifo_reset_rx 7.000s 886.871us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 102.000s 12771.739us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 29.000s 1429.066us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 4.000s 500.136us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 3.000s 1035.309us 0 1 0.00
target_stress_all 0 1 0.00
i2c_target_stress_all 3600.000s 0.000us 0 1 0.00
target_maxperf 1 1 100.00
i2c_target_perf 5.000s 1775.226us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 52.000s 3397.753us 1 1 100.00
i2c_target_intr_smoke 7.000s 1525.005us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 2.000s 199.273us 1 1 100.00
i2c_target_fifo_reset_tx 1.000s 252.704us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 9.000s 8422.724us 1 1 100.00
i2c_target_stress_rd 52.000s 3397.753us 1 1 100.00
i2c_target_intr_stress_wr 7.000s 7852.083us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 9.000s 5886.477us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 7.000s 3182.261us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 7.000s 1353.147us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 2.000s 209.027us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.000s 823.868us 1 1 100.00
i2c_target_fifo_watermarks_tx 2.000s 446.458us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 28.000s 4455.996us 1 1 100.00
i2c_host_perf_precise 9.000s 2901.557us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 29.000s 1429.066us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.000s 130.518us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 3.000s 930.935us 1 1 100.00
i2c_target_nack_acqfull_addr 4.000s 4525.398us 1 1 100.00
i2c_target_nack_txstretch 3.000s 568.064us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 11.000s 4185.950us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 5.000s 515.826us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 1.000s 44.852us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 2.000s 22.772us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.000s 417.262us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.000s 417.262us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 1.000s 25.502us 1 1 100.00
i2c_csr_rw 1.000s 36.492us 1 1 100.00
i2c_csr_aliasing 3.000s 419.866us 1 1 100.00
i2c_same_csr_outstanding 1.000s 41.828us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 1.000s 25.502us 1 1 100.00
i2c_csr_rw 1.000s 36.492us 1 1 100.00
i2c_csr_aliasing 3.000s 419.866us 1 1 100.00
i2c_same_csr_outstanding 1.000s 41.828us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 2.000s 134.761us 1 1 100.00
i2c_sec_cm 1.000s 63.299us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.000s 134.761us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 10.000s 3024.588us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 2.000s 303.257us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 1.000s 15.023us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
i2c_host_fifo_watermark 25584859642571627872058851135035068674888505985341158654313632943665960524311 None
i2c_host_stress_all 8487677875988280869391626910303578071309377307222157507853539839966651302565 None
i2c_target_stress_all 35890307450932932388726738454701463859795846988469988244304863029315136912363 None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_error_intr 2493275422840429768365387333971262927371256565721172279311238839212907091160 137
UVM_INFO @ 184043844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 92710592690875894012935839435923583107921458105354256612389102316587555921802 94
UVM_INFO @ 15022768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 4172629954318333349712866789702383919095086627442606102755144117640203769888 93
UVM_INFO @ 1035309339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 103609957474601154707452403979661776549689757518701946589310737634578161115247 87
UVM_INFO @ 303257295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 92894520665394196355781558448810591238226717756111123023209462512759874986994 97
UVM_INFO @ 3024588229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---