Simulation Results: lc_ctrl/volatile_unlock_disabled

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.01 %
  • code
  • 92.89 %
  • assert
  • 96.83 %
  • func
  • 86.31 %
  • block
  • 96.70 %
  • line
  • 97.42 %
  • branch
  • 91.61 %
  • toggle
  • 87.31 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
96.67%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 94.904us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 20.552us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 19.423us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 226.112us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 29.506us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 129.586us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 19.423us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 29.506us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 85.281us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 1472.574us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 17.230us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 84.048us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 253.038us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 1268.333us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 253.038us 1 1 100.00
lc_ctrl_prog_failure 3.000s 84.048us 1 1 100.00
lc_ctrl_errors 7.000s 1268.333us 1 1 100.00
lc_ctrl_security_escalation 6.000s 674.308us 1 1 100.00
lc_ctrl_jtag_state_failure 10.000s 888.978us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 7410.538us 1 1 100.00
lc_ctrl_jtag_errors 26.000s 25256.342us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 7.000s 2461.968us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.000s 344.115us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.000s 7410.538us 1 1 100.00
lc_ctrl_jtag_errors 26.000s 25256.342us 1 1 100.00
lc_ctrl_jtag_access 4.000s 663.539us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 21.000s 4719.058us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 105.366us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 89.350us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 982.494us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 1640.577us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 23.795us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.000s 249.533us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 61.040us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 31.000s 2007.425us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.782us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 31.000s 4762.474us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 16.831us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 69.872us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 69.872us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 20.552us 1 1 100.00
lc_ctrl_csr_rw 1.000s 19.423us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 29.506us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 52.394us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 20.552us 1 1 100.00
lc_ctrl_csr_rw 1.000s 19.423us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 29.506us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 52.394us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 3582.655us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 73.121us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 73.121us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 1472.574us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 253.038us 1 1 100.00
lc_ctrl_sec_cm 4.000s 3582.655us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 253.038us 1 1 100.00
lc_ctrl_sec_cm 4.000s 3582.655us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 253.038us 1 1 100.00
lc_ctrl_sec_cm 4.000s 3582.655us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 253.038us 1 1 100.00
lc_ctrl_sec_cm 4.000s 3582.655us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 253.038us 1 1 100.00
lc_ctrl_sec_cm 4.000s 3582.655us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 253.038us 1 1 100.00
lc_ctrl_sec_cm 4.000s 3582.655us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 253.038us 1 1 100.00
lc_ctrl_sec_cm 4.000s 3582.655us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 253.038us 1 1 100.00
lc_ctrl_sec_cm 4.000s 3582.655us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 674.308us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.000s 85.281us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.000s 344.115us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 707.350us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 707.350us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 5484.407us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 5020.114us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 5020.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 45.000s 5496.505us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_post_trans 74848568211812016474045185420720596500221792210999744857797333752271247147477 181
UVM_INFO @ 344114534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---