Simulation Results: lc_ctrl/volatile_unlock_enabled

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.99 %
  • code
  • 93.69 %
  • assert
  • 95.97 %
  • func
  • 86.31 %
  • block
  • 96.98 %
  • line
  • 97.54 %
  • branch
  • 92.33 %
  • toggle
  • 87.26 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 78.535us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 200.645us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 70.019us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 113.968us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 28.510us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 43.602us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 70.019us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 28.510us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 284.338us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 1291.658us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 40.455us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 1005.567us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.000s 5599.494us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 303.705us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.000s 5599.494us 1 1 100.00
lc_ctrl_prog_failure 3.000s 1005.567us 1 1 100.00
lc_ctrl_errors 6.000s 303.705us 1 1 100.00
lc_ctrl_security_escalation 4.000s 1366.503us 1 1 100.00
lc_ctrl_jtag_state_failure 19.000s 22414.942us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 590.009us 1 1 100.00
lc_ctrl_jtag_errors 26.000s 5170.996us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 494.985us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 910.668us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 590.009us 1 1 100.00
lc_ctrl_jtag_errors 26.000s 5170.996us 1 1 100.00
lc_ctrl_jtag_access 3.000s 298.945us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 18.000s 3252.051us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 97.772us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 77.028us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.000s 526.392us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 638.501us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 99.558us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 239.044us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 114.298us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 653.536us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 14.615us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 15.000s 1114.554us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 136.434us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 391.275us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 391.275us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 200.645us 1 1 100.00
lc_ctrl_csr_rw 1.000s 70.019us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 28.510us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 481.352us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 200.645us 1 1 100.00
lc_ctrl_csr_rw 1.000s 70.019us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 28.510us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 481.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 1580.744us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 161.101us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 161.101us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 1291.658us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 5599.494us 1 1 100.00
lc_ctrl_sec_cm 3.000s 1580.744us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 5599.494us 1 1 100.00
lc_ctrl_sec_cm 3.000s 1580.744us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.000s 5599.494us 1 1 100.00
lc_ctrl_sec_cm 3.000s 1580.744us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.000s 5599.494us 1 1 100.00
lc_ctrl_sec_cm 3.000s 1580.744us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 5599.494us 1 1 100.00
lc_ctrl_sec_cm 3.000s 1580.744us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 5599.494us 1 1 100.00
lc_ctrl_sec_cm 3.000s 1580.744us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 5599.494us 1 1 100.00
lc_ctrl_sec_cm 3.000s 1580.744us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.000s 5599.494us 1 1 100.00
lc_ctrl_sec_cm 3.000s 1580.744us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 1366.503us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 284.338us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 910.668us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 1945.140us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 1945.140us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 1671.069us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1225.301us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1225.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 26.000s 16405.952us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 55839490472098255469377762366912226283554181514111745401482492369860479207980 2043
UVM_INFO @ 16405951808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---