Simulation Results: mbx

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.88 %
  • code
  • 88.17 %
  • assert
  • 97.62 %
  • func
  • 83.85 %
  • block
  • 95.99 %
  • line
  • 95.47 %
  • branch
  • 89.37 %
  • toggle
  • 79.67 %
Validation stages
V1
100.00%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 36.000s 7191.713us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 55.181us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 25.230us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 2072.343us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 16.422us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 2.000s 48.783us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 25.230us 1 1 100.00
mbx_csr_aliasing 1.000s 16.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 93.000s 11640.261us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 2.000s 98.095us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 47.000s 24255.550us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 2917.320us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 59.033us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 63.080us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 15.298us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 15.298us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 55.181us 1 1 100.00
mbx_csr_rw 1.000s 25.230us 1 1 100.00
mbx_csr_aliasing 1.000s 16.422us 1 1 100.00
mbx_same_csr_outstanding 1.000s 18.721us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 55.181us 1 1 100.00
mbx_csr_rw 1.000s 25.230us 1 1 100.00
mbx_csr_aliasing 1.000s 16.422us 1 1 100.00
mbx_same_csr_outstanding 1.000s 18.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 300.597us 1 1 100.00
mbx_sec_cm 1.000s 22.447us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed 1 test run
mbx_stress_zero_delays 90597996512080318652701528444631975188748379947708361178260525132296381933502 152
UVM_ERROR @ 98094544 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 98094544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
mbx_tl_errors 108028986042019609521164557883761046304683356374323441301332754829090805237840 85
TL item was: req: (cip_tl_seq_item@17691) { a_addr: 'hf86a3650 a_data: 'h1af6e499 a_mask: 'h1 a_size: 'h2 a_param: 'h0 a_source: 'hb5 a_opcode: 'h1 a_user: 'h27659 d_param: 'h0 d_source: 'hb5 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 15297616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---