| V1 |
|
100.00% |
| V2 |
|
92.86% |
| V2S |
|
88.00% |
| V3 |
|
0.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 11.000s | 40.451us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 7.000s | 28.361us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 5.000s | 46.291us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 4.000s | 26.661us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 7.000s | 155.124us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 5.000s | 37.318us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 7.000s | 378.108us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 4.000s | 26.661us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 5.000s | 37.318us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 78.000s | 34758.630us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 50.000s | 1258.157us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 29.000s | 82.561us | 1 | 1 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 57.000s | 731.912us | 1 | 1 | 100.00 | |
| back_to_back | 0 | 1 | 0.00 | |||
| otbn_multi | 4.341s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 139.000s | 562.613us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 11.000s | 26.573us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 1 | 1 | 100.00 | |||
| otbn_zero_state_err_urnd | 5.000s | 16.514us | 1 | 1 | 100.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 7.000s | 85.256us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 7.000s | 19.846us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 5.000s | 44.340us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 4.000s | 82.747us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 4.000s | 82.747us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 5.000s | 46.291us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 4.000s | 26.661us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 5.000s | 37.318us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 85.954us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 5.000s | 46.291us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 4.000s | 26.661us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 5.000s | 37.318us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 85.954us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 1 | 2 | 50.00 | |||
| otbn_imem_err | 9.000s | 132.779us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 13.000s | 31.867us | 0 | 1 | 0.00 | |
| internal_integrity | 4 | 4 | 100.00 | |||
| otbn_alu_bignum_mod_err | 13.000s | 59.823us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 9.000s | 51.874us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 9.000s | 111.484us | 1 | 1 | 100.00 | |
| otbn_urnd_err | 6.000s | 21.009us | 1 | 1 | 100.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 8.000s | 17.280us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 7.000s | 28.678us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 1 | 1 | 100.00 | |||
| otbn_partial_wipe | 9.000s | 23.317us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| otbn_tl_intg_err | 29.000s | 195.734us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 26.000s | 269.595us | 1 | 1 | 100.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 11.000s | 40.451us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 0 | 1 | 0.00 | |||
| otbn_dmem_err | 13.000s | 31.867us | 0 | 1 | 0.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 9.000s | 132.779us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 29.000s | 195.734us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 11.000s | 26.573us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 3 | 5 | 60.00 | |||
| otbn_imem_err | 9.000s | 132.779us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 13.000s | 31.867us | 0 | 1 | 0.00 | |
| otbn_zero_state_err_urnd | 5.000s | 16.514us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 8.000s | 17.280us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_controller_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 7.000s | 28.361us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 3 | 5 | 60.00 | |||
| otbn_imem_err | 9.000s | 132.779us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 13.000s | 31.867us | 0 | 1 | 0.00 | |
| otbn_zero_state_err_urnd | 5.000s | 16.514us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 8.000s | 17.280us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 11.000s | 26.573us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 3 | 5 | 60.00 | |||
| otbn_imem_err | 9.000s | 132.779us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 13.000s | 31.867us | 0 | 1 | 0.00 | |
| otbn_zero_state_err_urnd | 5.000s | 16.514us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 8.000s | 17.280us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 7.000s | 28.361us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 8.000s | 19.655us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 7.000s | 13.157us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 38.000s | 130.718us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 38.000s | 130.718us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 6.000s | 39.460us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_bignum_intg_err | 8.000s | 50.899us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 18.000s | 40.746us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 18.000s | 40.746us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 12.000s | 71.195us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 7.000s | 28.361us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 7.000s | 28.361us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 7.000s | 28.361us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 0 | 1 | 0.00 | |||
| otbn_multi | 4.341s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 7.000s | 28.361us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 7.000s | 28.361us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 13.000s | 35.665us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 7.000s | 28.361us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 10.000s | 131.105us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otbn_stress_all_with_rand_reset | 237.000s | 4154.369us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| otbn_smoke_vectorized | 10.000s | 27.141us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 1 test run | |||
| otbn_multi | 110102117848269508233194561583435638190325761002014714669734462242936176122904 | None |
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
|
|
| UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error | 1 test run | |||
| otbn_dmem_err | 74510169927300899767722426387886085822510298655563970374755228855811359050373 | 120 |
UVM_INFO @ 31866894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| otbn_stress_all_with_rand_reset | 48424124224244980895306023079233952202191883045363770713498363142135088943853 | 250 |
UVM_INFO @ 4154368818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed | 1 test run | |||
| otbn_sec_cm | 91546791622489886858031352395265775006435286059268555206967866469465356411926 | 106 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 131105199 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 131105199 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 131105199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|