Simulation Results: otp_ctrl

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.46 %
  • code
  • 70.97 %
  • assert
  • 94.03 %
  • func
  • 55.39 %
  • line
  • 87.37 %
  • branch
  • 83.94 %
  • cond
  • 85.86 %
  • toggle
  • 61.67 %
  • FSM
  • 36.00 %
Validation stages
V1
88.89%
V2
60.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.630s 72.871us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.390s 1180.672us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.110s 1933.455us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.000s 741.230us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.800s 594.116us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 15.120s 6345.405us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.390s 72.699us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.000s 741.230us 1 1 100.00
otp_ctrl_csr_aliasing 15.120s 6345.405us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.460s 82.198us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.470s 646.296us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 147.900s 46433.530us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 1.630s 35.026us 0 1 0.00
partition_check 0 2 0.00
otp_ctrl_background_chks 3.800s 212.439us 0 1 0.00
otp_ctrl_check_fail 3.490s 325.233us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 5.600s 3059.082us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 5.250s 460.265us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 12.760s 567.140us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 21.690s 13412.229us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 30.350s 3015.322us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 4.710s 318.108us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 4.880s 562.159us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 22.700s 2222.522us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.610s 45.969us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.730s 187.720us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.470s 252.001us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.470s 252.001us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.110s 1933.455us 1 1 100.00
otp_ctrl_csr_rw 2.000s 741.230us 1 1 100.00
otp_ctrl_csr_aliasing 15.120s 6345.405us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.760s 362.001us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.110s 1933.455us 1 1 100.00
otp_ctrl_csr_rw 2.000s 741.230us 1 1 100.00
otp_ctrl_csr_aliasing 15.120s 6345.405us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.760s 362.001us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
otp_ctrl_tl_intg_err 23.800s 3874.082us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 23.800s 3874.082us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.390s 1180.672us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.390s 1180.672us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
otp_ctrl_macro_errs 4.710s 318.108us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
otp_ctrl_macro_errs 4.710s 318.108us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.170s 2351.237us 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 1.630s 35.026us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.490s 325.233us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 5.250s 460.265us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 5.250s 460.265us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 5.250s 460.265us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 5.250s 460.265us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 5.250s 460.265us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.390s 1180.672us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 5.250s 460.265us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.390s 1180.672us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 270.860s 64024.372us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 5.600s 3059.082us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.390s 1180.672us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.390s 1180.672us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 4.710s 318.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 88.170s 68781.830us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 103.290s 16077.375us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_background_chks 85828305930522902593434274608615167326157430118954740032719871032889351578768 3444
UVM_INFO @ 212439429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 23715280706790259458490495154895860281489595391369810901950791077660100304596 2800
UVM_INFO @ 460264589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 32392292672928292285393912012627900584512669100766919707951577219784865511043 1708
UVM_INFO @ 325232586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28841509891527219543028524997867838568883815884498400562411748039046306008072 28654
UVM_INFO @ 16077374795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 3 test runs
otp_ctrl_partition_walk 94996599506272185836395805665074146076136380462434919206486490607199720216461 160055
UVM_INFO @ 46433530417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 6098478446757859752060120251047190638425838870731565763741378013024800683427 199
UVM_INFO @ 35025844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 54913054610481058275467346412300068422935844299288565084686167714686557677048 4358
UVM_INFO @ 3059082283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_parallel_key_req 71469420381253479482059077469951201997959285673701797858372090343639371065693 7467
UVM_INFO @ 567139645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 35026240271701336003890974501986317204301377581031697238746539304535781205794 33406
UVM_INFO @ 2222522009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 88013583229935116345936218969879919347505510918942966839135545095860231324242 89
UVM_INFO @ 68781829991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 46394214597360791561579655801605469910942007483789761689754283435851911478477 97
UVM_INFO @ 72699395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---