Simulation Results: rom_ctrl/32kb

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.06 %
  • code
  • 93.71 %
  • assert
  • 97.53 %
  • func
  • 96.94 %
  • block
  • 96.15 %
  • line
  • 96.25 %
  • branch
  • 94.09 %
  • toggle
  • 84.49 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 175.748us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 477.300us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 172.966us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 384.597us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 275.812us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 175.541us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 172.966us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 275.812us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 169.701us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 1065.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.000s 731.416us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.000s 1678.953us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 2817.020us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 209.552us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 962.748us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 962.748us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 477.300us 1 1 100.00
rom_ctrl_csr_rw 3.000s 172.966us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 275.812us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 182.922us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 477.300us 1 1 100.00
rom_ctrl_csr_rw 3.000s 172.966us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 275.812us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 182.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.000s 1676.028us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 2622.285us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 103.000s 2768.078us 1 1 100.00
rom_ctrl_tl_intg_err 14.000s 629.691us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 103.000s 2768.078us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 103.000s 2768.078us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.000s 1676.028us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.000s 1676.028us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.000s 1676.028us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.000s 1676.028us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.000s 1676.028us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 103.000s 2768.078us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 103.000s 2768.078us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 175.748us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 175.748us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 175.748us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 14.000s 629.691us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.000s 1676.028us 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 2817.020us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.000s 1676.028us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.000s 1676.028us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.000s 1676.028us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 2622.285us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 103.000s 2768.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 36.000s 1762.745us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 2718003427210373888096962658806208715581521821812508406904371059211235917299 88
UVM_INFO @ 731415999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---