Simulation Results: rstmgr

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.74 %
  • code
  • 99.21 %
  • assert
  • 98.53 %
  • func
  • 95.48 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.41 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.320s 78.053us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.060s 93.044us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.090s 37.693us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.880s 135.597us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.510s 51.781us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.050s 67.342us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.090s 37.693us 1 1 100.00
rstmgr_csr_aliasing 1.510s 51.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.220s 110.771us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.260s 47.735us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.170s 99.605us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.440s 679.293us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.440s 679.293us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.440s 679.293us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.440s 679.293us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 31.250s 5210.325us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.890s 36.919us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.760s 46.107us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.760s 46.107us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.060s 93.044us 1 1 100.00
rstmgr_csr_rw 1.090s 37.693us 1 1 100.00
rstmgr_csr_aliasing 1.510s 51.781us 1 1 100.00
rstmgr_same_csr_outstanding 1.140s 46.447us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.060s 93.044us 1 1 100.00
rstmgr_csr_rw 1.090s 37.693us 1 1 100.00
rstmgr_csr_aliasing 1.510s 51.781us 1 1 100.00
rstmgr_same_csr_outstanding 1.140s 46.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 15.410s 3403.189us 1 1 100.00
rstmgr_tl_intg_err 5.650s 628.820us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 15.410s 3403.189us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 15.410s 3403.189us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 5.650s 628.820us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.160s 54.219us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.010s 467.735us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.290s 291.170us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 15.410s 3403.189us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.090s 37.693us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.090s 37.693us 1 1 100.00